forked from Github_Repos/cvw
cc1ba84637
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes. |
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| .. | ||
| wallypipelinedcore.sv | ||
| wallypipelinedsoc.sv | ||
| wallypipelinedsocwrapper.v | ||