Ross Thompson 37079626cd Fixed numerous errors in the preformance counter updates. ... Fixed dcache reporting of access and misses. Added performance counter tracking to coremark.		2021-12-09 11:44:12 -06:00
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cachereplacementpolicy.sv	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
cacheway.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
dcache_ptw_interaction_README.txt	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
dcache.sv	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
dcachefsm.sv	Fixed numerous errors in the preformance counter updates.	2021-12-09 11:44:12 -06:00
icache.sv	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
icachefsm.sv	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
sram1rw.sv	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00