cvw/fpga/generator/debug/load-deadlock.tsm

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##################################################
#
# For info on creating trigger state machines:
# 1) In the main Vivado menu bar, select
# Window > Language Templates
# 2) In the Templates window, select
# Debug > Trigger State Machine
# 3) Refer to the entry 'Info' for an overview
# of the trigger state machine language.
#
# More information can be found in this document:
#
# Vivado Design Suite User Guide: Programming
# and Debugging (UG908)
#
##################################################
state state_reset:
if(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
reset_counter $counter0;
goto state_begin_count;
#goto state_trigger;
else
goto state_reset;
endif
state state_begin_count:
if($counter0 == 16'h0264) then
goto state_trigger;
elseif(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
increment_counter $counter0;
goto state_begin_count;
else
goto state_reset;
endif
state state_trigger:
trigger;