forked from Github_Repos/cvw
63 lines
2.2 KiB
Systemverilog
63 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: James Stine
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// Modified: 8/1/2018
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//
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// Purpose: Bipartite Lookup for divide portion of fpdivsqrt
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module sbtm_div (input logic [11:0] a, output logic [10:0] ia_out);
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// bit partitions
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logic [3:0] x0;
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logic [2:0] x1;
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logic [3:0] x2;
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logic [2:0] x2_1cmp;
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// mem outputs
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logic [12:0] y0;
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logic [4:0] y1;
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// input to CPA
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logic [14:0] op1;
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logic [14:0] op2;
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logic [14:0] p;
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logic cout;
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assign x0 = a[10:7];
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assign x1 = a[6:4];
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assign x2 = a[3:0];
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sbtm_a0 mem1 ({x0, x1}, y0);
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// 1s cmp per sbtm/stam
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assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
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sbtm_a1 mem2 ({x0, x2_1cmp}, y1);
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assign op1 = {1'b0, y0, 1'b0};
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// 1s cmp per sbtm/stam
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assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} :
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{1'b0, 8'b0, y1, 1'b1};
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// CPA
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assign {cout, p} = op1 + op2;
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assign ia_out = p[14:4];
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endmodule // sbtm
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