forked from Github_Repos/cvw
43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
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`include "wally-config.vh"
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module fclassify (
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input logic XSgnE, // sign bit
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input logic XNaNE, // is NaN
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input logic XSNaNE, // is signaling NaN
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input logic XNormE, // is normal
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input logic XDenormE, // is denormal
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input logic XZeroE, // is zero
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input logic XInfE, // is infinity
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output logic [63:0] ClassResE // classify result
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);
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logic PInf, PZero, PNorm, PDenorm;
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logic NInf, NZero, NNorm, NDenorm;
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// determine the sub categories
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assign PInf = ~XSgnE&XInfE;
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assign NInf = XSgnE&XInfE;
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assign PNorm = ~XSgnE&XNormE;
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assign NNorm = XSgnE&XNormE;
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assign PDenorm = ~XSgnE&XDenormE;
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assign NDenorm = XSgnE&XDenormE;
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assign PZero = ~XSgnE&XZeroE;
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assign NZero = XSgnE&XZeroE;
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// determine sub category and combine into the result
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// bit 0 - -Inf
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// bit 1 - -Norm
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// bit 2 - -Denorm
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// bit 3 - -Zero
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// bit 4 - +Zero
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// bit 5 - +Denorm
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// bit 6 - +Norm
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// bit 7 - +Inf
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// bit 8 - signaling NaN
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// bit 9 - quiet NaN
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assign ClassResE = {{54{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
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endmodule
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