forked from Github_Repos/cvw
21 lines
590 B
Plaintext
21 lines
590 B
Plaintext
#--showoverrides
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--override cpu/unaligned=F
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--override refRoot/cpu/mstatus_FS=1
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# Enable the Imperas instruction coverage
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-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
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-override refRoot/cpu/cv/cover=basic
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-override refRoot/cpu/cv/extensions=RV32I
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# Add Imperas simulator application instruction tracing
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--trace
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--tracechange
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--traceshowicount
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--tracemode
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--monitornetschange
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# Turn on verbose output for Imperas simulator
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--verbose
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# Turn on verbose output for RISCV model
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--override cpu/verbose=1
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# Store simulator output to logfile
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--output imperas.log
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