forked from Github_Repos/cvw
74 lines
1.7 KiB
Systemverilog
74 lines
1.7 KiB
Systemverilog
/* -----\/----- EXCLUDED -----\/-----
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// Depth is number of bits in one "word" of the memory, width is number of such words
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/-* verilator lint_off ASSIGNDLY *-/
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module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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// port 1 is read only
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input logic [$clog2(WIDTH)-1:0] Addr,
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output logic [DEPTH-1:0] ReadData,
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// port 2 is write only
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input logic [DEPTH-1:0] WriteData,
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input logic WriteEnable
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);
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logic [WIDTH-1:0][DEPTH-1:0] StoredData;
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logic [$clog2(WIDTH)-1:0] AddrD;
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always_ff @(posedge clk) begin
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AddrD <= Addr;
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if (WriteEnable) begin
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StoredData[Addr] <= #1 WriteData;
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end
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end
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assign ReadData = StoredData[AddrD];
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endmodule
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/-* verilator lint_on ASSIGNDLY *-/
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-----/\----- EXCLUDED -----/\----- */
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// Depth is number of bits in one "word" of the memory, width is number of such words
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/* verilator lint_off ASSIGNDLY */
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module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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// port 1 is read only
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input logic [$clog2(WIDTH)-1:0] Addr,
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output logic [DEPTH-1:0] ReadData,
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// port 2 is write only
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input logic [DEPTH-1:0] WriteData,
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input logic WriteEnable
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);
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logic [WIDTH-1:0][DEPTH-1:0] StoredData;
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logic [$clog2(WIDTH)-1:0] AddrD;
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logic [WIDTH-1:0] WriteDataD;
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logic WriteEnableD;
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always_ff @(posedge clk) begin
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AddrD <= Addr;
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WriteDataD <= WriteData;
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WriteEnableD <= WriteEnable;
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if (WriteEnableD) begin
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StoredData[AddrD] <= #1 WriteDataD;
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end
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end
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assign ReadData = StoredData[AddrD];
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endmodule
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/* verilator lint_on ASSIGNDLY */
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