forked from Github_Repos/cvw
226 lines
4.0 KiB
ArmAsm
226 lines
4.0 KiB
ArmAsm
# See LICENSE for license details.
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#include "encoding.h"
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#if __riscv_xlen == 64
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# define LREG ld
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# define SREG sd
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# define REGBYTES 8
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#else
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# define LREG lw
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# define SREG sw
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# define REGBYTES 4
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#endif
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.section ".text.init"
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.globl _start
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_start:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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# enable FPU and accelerator if present
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li t0, MSTATUS_FS | MSTATUS_XS
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csrs mstatus, t0
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# make sure XLEN agrees with compilation choice
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li t0, 1
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slli t0, t0, 31
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#if __riscv_xlen == 64
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bgez t0, 1f
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#else
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bltz t0, 1f
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#endif
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2:
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li a0, 1
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sw a0, tohost, t0
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j 2b
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1:
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#ifdef __riscv_flen
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# initialize FPU if we have one
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la t0, 1f
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csrw mtvec, t0
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fssr x0
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fmv.s.x f0, x0
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fmv.s.x f1, x0
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fmv.s.x f2, x0
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fmv.s.x f3, x0
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fmv.s.x f4, x0
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fmv.s.x f5, x0
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fmv.s.x f6, x0
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fmv.s.x f7, x0
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fmv.s.x f8, x0
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fmv.s.x f9, x0
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fmv.s.x f10,x0
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fmv.s.x f11,x0
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fmv.s.x f12,x0
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fmv.s.x f13,x0
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fmv.s.x f14,x0
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fmv.s.x f15,x0
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fmv.s.x f16,x0
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fmv.s.x f17,x0
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fmv.s.x f18,x0
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fmv.s.x f19,x0
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fmv.s.x f20,x0
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fmv.s.x f21,x0
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fmv.s.x f22,x0
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fmv.s.x f23,x0
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fmv.s.x f24,x0
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fmv.s.x f25,x0
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fmv.s.x f26,x0
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fmv.s.x f27,x0
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fmv.s.x f28,x0
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fmv.s.x f29,x0
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fmv.s.x f30,x0
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fmv.s.x f31,x0
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1:
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#endif
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# initialize trap vector
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la t0, trap_entry
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csrw mtvec, t0
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# initialize global pointer
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la tp, _end + 63
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and tp, tp, -64
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# get core id
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csrr a0, mhartid
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# for now, assume only 1 core
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li a1, 1
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1:bgeu a0, a1, 1b
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# give each core 128KB of stack + TLS
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#define STKSHIFT 17
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add sp, a0, 1
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sll sp, sp, STKSHIFT
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add sp, sp, tp
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sll a2, a0, STKSHIFT
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add tp, tp, a2
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j _init
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.align 2
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trap_entry:
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addi sp, sp, -272
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SREG x1, 1*REGBYTES(sp)
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SREG x2, 2*REGBYTES(sp)
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SREG x3, 3*REGBYTES(sp)
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SREG x4, 4*REGBYTES(sp)
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SREG x5, 5*REGBYTES(sp)
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SREG x6, 6*REGBYTES(sp)
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SREG x7, 7*REGBYTES(sp)
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SREG x8, 8*REGBYTES(sp)
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SREG x9, 9*REGBYTES(sp)
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SREG x10, 10*REGBYTES(sp)
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SREG x11, 11*REGBYTES(sp)
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SREG x12, 12*REGBYTES(sp)
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SREG x13, 13*REGBYTES(sp)
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SREG x14, 14*REGBYTES(sp)
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SREG x15, 15*REGBYTES(sp)
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SREG x16, 16*REGBYTES(sp)
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SREG x17, 17*REGBYTES(sp)
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SREG x18, 18*REGBYTES(sp)
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SREG x19, 19*REGBYTES(sp)
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SREG x20, 20*REGBYTES(sp)
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SREG x21, 21*REGBYTES(sp)
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SREG x22, 22*REGBYTES(sp)
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SREG x23, 23*REGBYTES(sp)
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SREG x24, 24*REGBYTES(sp)
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SREG x25, 25*REGBYTES(sp)
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SREG x26, 26*REGBYTES(sp)
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SREG x27, 27*REGBYTES(sp)
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SREG x28, 28*REGBYTES(sp)
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SREG x29, 29*REGBYTES(sp)
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SREG x30, 30*REGBYTES(sp)
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SREG x31, 31*REGBYTES(sp)
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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jal handle_trap
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csrw mepc, a0
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# Remain in M-mode after eret
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li t0, MSTATUS_MPP
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csrs mstatus, t0
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LREG x1, 1*REGBYTES(sp)
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LREG x2, 2*REGBYTES(sp)
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LREG x3, 3*REGBYTES(sp)
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LREG x4, 4*REGBYTES(sp)
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LREG x5, 5*REGBYTES(sp)
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LREG x6, 6*REGBYTES(sp)
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LREG x7, 7*REGBYTES(sp)
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LREG x8, 8*REGBYTES(sp)
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LREG x9, 9*REGBYTES(sp)
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LREG x10, 10*REGBYTES(sp)
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LREG x11, 11*REGBYTES(sp)
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LREG x12, 12*REGBYTES(sp)
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LREG x13, 13*REGBYTES(sp)
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LREG x14, 14*REGBYTES(sp)
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LREG x15, 15*REGBYTES(sp)
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LREG x16, 16*REGBYTES(sp)
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LREG x17, 17*REGBYTES(sp)
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LREG x18, 18*REGBYTES(sp)
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LREG x19, 19*REGBYTES(sp)
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LREG x20, 20*REGBYTES(sp)
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LREG x21, 21*REGBYTES(sp)
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LREG x22, 22*REGBYTES(sp)
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LREG x23, 23*REGBYTES(sp)
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LREG x24, 24*REGBYTES(sp)
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LREG x25, 25*REGBYTES(sp)
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LREG x26, 26*REGBYTES(sp)
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LREG x27, 27*REGBYTES(sp)
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LREG x28, 28*REGBYTES(sp)
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LREG x29, 29*REGBYTES(sp)
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LREG x30, 30*REGBYTES(sp)
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LREG x31, 31*REGBYTES(sp)
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addi sp, sp, 272
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mret
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.section ".tohost","aw",@progbits
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.align 6
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.globl tohost
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tohost: .dword 0
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.align 6
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.globl fromhost
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fromhost: .dword 0
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