cvw/pipelined/regression
2022-02-17 16:20:20 -06:00
..
slack-notifier
wave-dos
buildrootBugFinder.py update bugfinder script to new file organization 2022-02-15 22:58:18 +00:00
fpga-wave.do More cache cleanup. 2022-02-13 15:47:27 -06:00
lint-wally Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
linux-wave.do Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
sim-buildroot Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
sim-buildroot-batch Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally
sim-wally-batch Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
wally-pipelined-fpga.do
wally-pipelined.do Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
wave-all.do
wave-coremark.do More cache cleanup. 2022-02-13 15:47:27 -06:00
wave.do Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00