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Configurable RISC-V Processor
305 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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David Harris eaef379454 Drafted AMO tests
2021-03-11 00:42:13 -05:00
sky130
wally-pipelined Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
.gitignore add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor