forked from Github_Repos/cvw
164 lines
6.8 KiB
Systemverilog
164 lines
6.8 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtpreproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtpreproc (
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input logic clk,
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input logic IFDivStartE,
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input logic [`NF:0] Xm, Ym,
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input logic [`NE-1:0] Xe, Ye,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic XZeroE,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E,
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input logic MDUE, W64E,
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output logic [`DIVBLEN:0] nE, nM, mM,
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output logic NegQuotM, ALTBM, MDUM, W64M,
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output logic AsM, AZeroM, BZeroM, AZeroE, BZeroE,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb+3:0] X,
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output logic [`DIVb-1:0] DPreproc,
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output logic [`XLEN-1:0] AM
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);
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logic [`DIVb-1:0] XPreproc;
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logic [`DIVb:0] SqrtX;
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logic [`DIVb+3:0] DivX;
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logic [`NE+1:0] QeE;
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// Intdiv signals
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
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logic [`LOGRK:0] pPrTrunc;
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logic [`DIVb+3:0] PreShiftX;
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logic NumZeroE;
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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if (`IDIV_ON_FPU) begin
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logic signedDiv;
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logic AsE, BsE, ALTBE, NegQuotE;
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logic [`XLEN-1:0] AE, BE;
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logic [`XLEN-1:0] PosA, PosB;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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if (`XLEN==64) begin // 64-bit, supports W64
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assign AsE = signedDiv & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
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assign BsE = signedDiv & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
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assign AE = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
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assign BE = W64E ? {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
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assign AZeroE = W64E ? ~(|ForwardedSrcAE[31:0]) : ~(|ForwardedSrcAE);
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assign BZeroE = W64E ? ~(|ForwardedSrcBE[31:0]) : ~(|ForwardedSrcBE);
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end else begin // 32 bits only
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assign AsE = signedDiv & ForwardedSrcAE[`XLEN-1];
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assign BsE = signedDiv & ForwardedSrcBE[`XLEN-1];
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assign AE = ForwardedSrcAE;
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assign BE = ForwardedSrcBE;
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assign AZeroE = ~(|ForwardedSrcAE);
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assign BZeroE = ~(|ForwardedSrcBE);
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end
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// Quotient is negative
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assign NegQuotE = (AsE ^ BsE) & MDUE;
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// Force inputs to be postiive
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assign PosA = AsE ? -AE : AE;
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assign PosB = BsE ? -BE : BE;
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// Select integer or floating point inputs
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assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
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// Difference in number of leading zeros
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assign ZeroDiff = mE - ell;
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assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
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assign p = ALTBE ? '0 : ZeroDiff;
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/* verilator lint_off WIDTH */
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// right shift amount to complete in discrete number of steps
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assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
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assign pPrTrunc = pPlusr % `RK;
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assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
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assign nE = (pPrCeil * (`DIVBLEN+1)'(`DIVCOPIES)) - {{(`DIVBLEN){1'b0}}, 1'b1};
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assign IntBits = (`DIVBLEN)'(`LOGR) + p - {{(`DIVBLEN){1'b0}}, 1'b1};
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assign RightShiftX = ((`DIVBLEN)'(`RK) - 1) - (IntBits % `RK);
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/* verilator lint_on WIDTH */
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// Selet integer or floating-point operands
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assign NumZeroE = MDUE ? AZeroE : XZeroE;
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assign X = MDUE ? DivX >> RightShiftX : PreShiftX;
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// pipeline registers
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flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM);
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
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flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
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end else begin
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assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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assign NumZeroE = XZeroE;
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assign X = PreShiftX;
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end
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// count leading zeros for denorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFNormLenX, ell);
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lzc #(`DIVb) lzcY (IFNormLenD, mE);
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// Normalization shift
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1});
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for nonzero inputs) and zero-extend
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assign SqrtX = (Xe[0]^ell[0]) ? {1'b0, ~NumZeroE, XPreproc[`DIVb-1:1]} : {~NumZeroE, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF
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assign DivX = {3'b000, ~NumZeroE, XPreproc};
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// *** explain why X is shifted between radices (initial assignment of WS=RX)
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if (`RADIX == 2) assign PreShiftX = Sqrt ? {3'b111, SqrtX} : DivX;
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else assign PreShiftX = Sqrt ? {2'b11, SqrtX, 1'b0} : DivX;
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// Floating-point exponent
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fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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endmodule
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