forked from Github_Repos/cvw
e7288716f7
Added parameterized PCSTART to allow compatibility between imperas and busybear tests Hopefully we are done with the "busybear" branch, please don't use it for future work
170 lines
7.0 KiB
Systemverilog
170 lines
7.0 KiB
Systemverilog
///////////////////////////////////////////
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// datapath.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Datapath
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module datapath #(parameter PCSTART = 32'h80000000) (
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input logic clk, reset,
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// Fetch stage signals
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input logic StallF,
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output logic [`XLEN-1:0] PCF,
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input logic [31:0] InstrF,
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// Decode stage signals
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output logic [6:0] OpD,
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output logic [2:0] Funct3D,
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output logic Funct7b5D,
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input logic StallD, FlushD,
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input logic [2:0] ImmSrcD,
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input logic LoadStallD, // for performance counter
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output logic IllegalCompInstrD,
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// Execute stage signals
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input logic FlushE,
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input logic [1:0] ForwardAE, ForwardBE,
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input logic PCSrcE,
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input logic [4:0] ALUControlE,
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input logic ALUSrcAE, ALUSrcBE,
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input logic TargetSrcE,
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output logic [2:0] FlagsE,
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// Memory stage signals
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input logic FlushM,
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input logic [1:0] MemRWM,
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input logic CSRWriteM, PrivilegedM,
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input logic InstrAccessFaultM, IllegalInstrFaultM,
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input logic TimerIntM, ExtIntM, SwIntM,
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output logic InstrMisalignedFaultM,
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input logic [2:0] Funct3M,
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output logic [`XLEN-1:0] WriteDataM, ALUResultM,
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input logic [`XLEN-1:0] ReadDataM,
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output logic [7:0] ByteMaskM,
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output logic RetM, TrapM,
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input logic [4:0] SetFflagsM,
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input logic DataAccessFaultM,
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// Writeback stage signals
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input logic FlushW,
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input logic RegWriteW,
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input logic [1:0] ResultSrcW,
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input logic InstrValidW,
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input logic FloatRegWriteW,
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output logic [2:0] FRM_REGW,
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// Hazard Unit signals
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output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
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output logic [4:0] RdE, RdM, RdW);
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// Fetch stage signals
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logic [`XLEN-1:0] PCPlus2or4F;
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// Decode stage signals
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logic [31:0] InstrD;
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logic [`XLEN-1:0] PCD, PCPlus2or4D;
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logic [`XLEN-1:0] RD1D, RD2D;
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logic [`XLEN-1:0] ExtImmD;
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logic [31:0] InstrDecompD;
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logic [4:0] RdD;
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// Execute stage signals
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logic [31:0] InstrE;
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logic [`XLEN-1:0] RD1E, RD2E;
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logic [`XLEN-1:0] PCE, ExtImmE;
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logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
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logic [`XLEN-1:0] ALUResultE;
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logic [`XLEN-1:0] WriteDataE;
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logic [`XLEN-1:0] TargetBaseE;
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// Memory stage signals
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logic [31:0] InstrM;
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logic [`XLEN-1:0] PCM;
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logic [`XLEN-1:0] SrcAM;
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logic [`XLEN-1:0] ReadDataExtM;
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logic [`XLEN-1:0] WriteDataFullM;
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logic [`XLEN-1:0] CSRReadValM;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreMisalignedFaultM, StoreAccessFaultM;
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logic [`XLEN-1:0] InstrMisalignedAdrM;
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// Writeback stage signals
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logic [`XLEN-1:0] ALUResultW;
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logic [`XLEN-1:0] ReadDataW;
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logic [`XLEN-1:0] PCW;
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logic [`XLEN-1:0] CSRValW;
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logic [`XLEN-1:0] ResultW;
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logic [31:0] nop = 32'h00000013; // instruction for NOP
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// Fetch stage pipeline register and logic; also Ex stage for branches
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pclogic #(PCSTART) pclogic(.*);
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// Decode stage pipeline register and logic
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flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD);
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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flopenrc #(`XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D);
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instrDecompress decomp(.*);
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assign OpD = InstrDecompD[6:0];
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assign Funct3D = InstrDecompD[14:12];
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assign Funct7b5D = InstrDecompD[30];
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assign Rs1D = InstrDecompD[19:15];
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assign Rs2D = InstrDecompD[24:20];
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assign RdD = InstrDecompD[11:7];
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regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
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extend ext(.InstrDecompD(InstrDecompD[31:7]), .*);
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// Execute stage pipeline register and logic
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floprc #(`XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E);
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floprc #(`XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E);
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floprc #(`XLEN) PCEReg(clk, reset, FlushE, PCD, PCE);
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floprc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE);
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flopr #(32) InstrEReg(clk, reset, FlushE ? nop : InstrDecompD, InstrE);
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floprc #(5) Rs1EReg(clk, reset, FlushE, Rs1D, Rs1E);
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floprc #(5) Rs2EReg(clk, reset, FlushE, Rs2D, Rs2E);
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floprc #(5) RdEReg(clk, reset, FlushE, RdD, RdE);
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mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
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mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
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mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE);
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mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
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// Memory stage pipeline register
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floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
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floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
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floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM);
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floprc #(`XLEN) PCMReg(clk, reset, FlushM, PCE, PCM);
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flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM);
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floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM);
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memdp memdp(.AdrM(ALUResultM), .*);
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// Priveleged block operates in M and W stages, handling CSRs and exceptions
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privileged priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*);
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// Writeback stage pipeline register and logic
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floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
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floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW);
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floprc #(`XLEN) PCWReg(clk, reset, FlushW, PCM, PCW);
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floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW);
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floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW);
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mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW);
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endmodule
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