cvw/pipelined/regression
2022-02-11 13:28:18 -06:00
..
slack-notifier
wave-dos Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
buildrootBugFinder.py
fpga-wave.do cache cleanup 2022-02-03 15:36:11 +00:00
lint-wally Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
linux-wave.do Updates to linux wave. 2022-02-11 13:28:18 -06:00
make-tests.sh
Makefile Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 2022-02-03 08:32:48 -06:00
makefile-memfile Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 2022-02-03 08:32:48 -06:00
regression-wally Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
sim-buildroot Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
sim-buildroot-batch Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
sim-wally-batch Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
wally-pipelined-fpga.do
wally-pipelined.do Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
wave-all.do Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
wave-coremark.do cache cleanup 2022-02-03 15:36:11 +00:00
wave.do Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00