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Configurable RISC-V Processor
1,487 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
e1a1a8395e
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David Harris e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
riscv-coremark Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use 2021-07-14 04:46:11 -04:00
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wally-pipelined Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
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.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor