forked from Github_Repos/cvw
80 lines
1.6 KiB
Systemverilog
80 lines
1.6 KiB
Systemverilog
`include "idiv-config.vh"
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module tb;
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logic [31:0] N, D;
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logic clk;
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logic reset;
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logic start;
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logic S;
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logic [31:0] Q;
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logic [31:0] rem0;
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logic div0;
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logic done;
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integer handle3;
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integer desc3;
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integer i;
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logic [31:0] Ncomp;
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logic [31:0] Dcomp;
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logic [31:0] Qcomp;
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logic [31:0] Rcomp;
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logic [31:0] vectornum;
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logic [31:0] errors;
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intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
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initial
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begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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initial
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begin
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vectornum = 0;
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errors = 0;
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handle3 = $fopen("iter32_signed.out");
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end
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always @(posedge clk, posedge reset)
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begin
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desc3 = handle3;
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#0 start = 1'b0;
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#0 S = 1'b1;
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#0 reset = 1'b1;
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#30 reset = 1'b0;
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#30 N = 32'h0;
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#0 D = 32'h0;
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for (i=0; i<`IDIV_TESTS; i=i+1)
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begin
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N = $urandom;
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D = $urandom;
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start <= 1'b1;
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// Wait 2 cycles (to be sure)
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repeat (2)
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@(posedge clk);
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start <= 1'b0;
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repeat (41)
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@(posedge clk);
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Ncomp = N;
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Dcomp = D;
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Qcomp = $signed(Ncomp)/$signed(Dcomp);
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Rcomp = $signed(Ncomp)%$signed(Dcomp);
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if ((Q !== Qcomp)) begin
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
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N, D, Q, rem0, Qcomp, Rcomp,
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(Q==Qcomp), (rem0==Rcomp));
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end // for (i=0; i<2, i=i+1)
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$display("%d tests completed, %d errors", vectornum, errors);
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$finish;
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end
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endmodule // tb
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