forked from Github_Repos/cvw
94 lines
3.5 KiB
ArmAsm
94 lines
3.5 KiB
ArmAsm
///////////////////////////////////////////
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//
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// WALLY-trap-u
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-03-11
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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RVTEST_ISA("RV32I")
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
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INIT_TESTS
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CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
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// test 5.3.1.4 Basic trap tests
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TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps
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TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well
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// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
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li x28, 0x2
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csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
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li x28, 0x8
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csrc mstatus, x28 // clear mstatus.MIE bit
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WRITE_READ_CSR mie, 0xFFFF
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GOTO_U_MODE
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// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
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jal cause_instr_access
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jal cause_illegal_instr
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jal cause_breakpnt
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jal cause_load_addr_misaligned
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jal cause_load_acc
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jal cause_store_addr_misaligned
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jal cause_store_acc
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jal cause_ecall
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// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
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jal cause_m_soft_interrupt
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jal cause_m_time_interrupt
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li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
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// since interrupts are not always enabled,
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jal cause_s_ext_interrupt_GPIO
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li a3, 0x40
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jal cause_m_ext_interrupt
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// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
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// We can tell which one becuase the different trap handler modes write different bits of the status register
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// to the output when EXT_SIGNATURE is on.
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GOTO_M_MODE // so we can write the delegate registers
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WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
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WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
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GOTO_U_MODE
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jal cause_instr_access
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jal cause_illegal_instr
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jal cause_breakpnt
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jal cause_load_addr_misaligned
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jal cause_load_acc
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jal cause_store_addr_misaligned
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jal cause_store_acc
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jal cause_ecall
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// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
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li a3, 0x40
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jal cause_s_ext_interrupt_GPIO
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END_TESTS
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TEST_STACK_AND_DATA
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