forked from Github_Repos/cvw
427 lines
19 KiB
Systemverilog
Executable File
427 lines
19 KiB
Systemverilog
Executable File
//
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// File name : fpadd
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// Title : Floating-Point Adder/Subtractor
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// project : FPU
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// Library : fpadd
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// Author(s) : James E. Stine, Jr., Brett Mathis
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// Purpose : definition of main unit to floating-point add/sub
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// notes :
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//
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// Copyright Oklahoma State University
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// Copyright AFRL
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//
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// Basic and Denormalized Operations
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//
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// Step 1: Load operands, set flags, and convert SP to DP
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// Step 2: Check for special inputs ( +/- Infinity, NaN)
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// Step 3: Compare exponents. Swap the operands of exp1 < exp2
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// or of (exp1 = exp2 AND mnt1 < mnt2)
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// Step 4: Shift the mantissa corresponding to the smaller exponent,
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// and extend precision by three bits to the right.
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// Step 5: Add or subtract the mantissas.
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// Step 6: Normalize the result.//
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// Shift left until normalized. Normalized when the value to the
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// left of the binrary point is 1.
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// Step 7: Round the result.//
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// Step 8: Put sum onto output.
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//
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module faddcvt(
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input logic clk,
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input logic reset,
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input logic FlushM, // flush the memory stage
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input logic StallM, // stall the memory stage
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input logic [63:0] FSrcXE, // 1st input operand (A)
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input logic [63:0] FSrcYE, // 2nd input operand (B)
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input logic [2:0] FOpCtrlE, FOpCtrlM, // Function opcode
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input logic FmtE, FmtM, // Result Precision (0 for double, 1 for single)
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input logic [2:0] FrmM, // Rounding mode - specify values
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input logic XSgnE, YSgnE,
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input logic [52:0] XManE, YManE,
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input logic [10:0] XExpE, YExpE,
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input logic XSgnM, YSgnM,
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input logic [52:0] XManM, YManM,
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input logic [10:0] XExpM, YExpM,
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input logic XDenormE, YDenormE,
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input logic XNormE, YNormE,
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input logic XNormM, YNormM,
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input logic XZeroE, YZeroE,
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input logic XInfE, YInfE,
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input logic XNaNE, YNaNE,
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input logic XSNaNE, YSNaNE,
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output logic [63:0] FAddResM, // Result of operation
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output logic [4:0] FAddFlgM); // IEEE exception flags
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logic [63:0] AddSumE, AddSumM;
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logic [63:0] AddSumTcE, AddSumTcM;
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logic [3:0] AddSelInvE, AddSelInvM;
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logic [10:0] AddExpPostSumE,AddExpPostSumM;
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logic AddCorrSignE, AddCorrSignM;
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logic AddOpANormE, AddOpANormM;
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logic AddOpBNormE, AddOpBNormM;
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logic AddInvalidE, AddInvalidM;
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logic AddDenormInE, AddDenormInM;
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logic AddSwapE, AddSwapM;
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logic AddSignAE, AddSignAM;
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logic [11:0] AddExp1DenormE, AddExp2DenormE, AddExp1DenormM, AddExp2DenormM;
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logic [10:0] AddExponentE, AddExponentM;
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fpuaddcvt1 fpadd1 (.FOpCtrlE, .FmtE, .AddExponentE,
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.AddExpPostSumE, .AddExp1DenormE, .AddExp2DenormE, .AddSumE, .AddSumTcE, .AddSelInvE,
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.XSgnE, .YSgnE,.XManE, .YManE, .XExpE, .YExpE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE,
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.AddCorrSignE, .AddSignAE, .AddOpANormE, .AddOpBNormE, .AddInvalidE,
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.AddDenormInE, .AddSwapE);
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// E/M pipeline registers
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flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM);
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flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM);
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flopenrc #(11) EMRegAdd3(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM);
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flopenrc #(12) EMRegAdd6(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM);
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flopenrc #(12) EMRegAdd7(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM);
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flopenrc #(11) EMRegAdd8(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM);
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flopenrc #(11) EMRegAdd9(clk, reset, FlushM, ~StallM,
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{AddSelInvE, AddCorrSignE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddSwapE, AddSignAE},
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{AddSelInvM, AddCorrSignM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddSwapM, AddSignAM});
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fpuaddcvt2 fpadd2 (.FrmM, .FOpCtrlM, .FmtM, .AddSumM, .AddSumTcM, .XNormM, .YNormM,
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.AddExp1DenormM, .AddExp2DenormM, .AddExponentM, .AddExpPostSumM, .AddSelInvM, .XSgnM, .YSgnM, .XManM, .YManM, .XExpM, .YExpM,
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.AddOpANormM, .AddOpBNormM, .AddInvalidM, .AddDenormInM,
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.AddSignAM, .AddCorrSignM, .AddSwapM, .FAddResM, .FAddFlgM);
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endmodule
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module fpuaddcvt1 (
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input logic [2:0] FOpCtrlE, // Function opcode
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input logic FmtE, // Result Precision (1 for double, 0 for single)
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input logic XSgnE, YSgnE,
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input logic [10:0] XExpE, YExpE,
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input logic [52:0] XManE, YManE,
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input logic XDenormE, YDenormE,
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input logic XNormE, YNormE,
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input logic XZeroE, YZeroE,
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input logic XInfE, YInfE,
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input logic XNaNE, YNaNE,
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input logic XSNaNE, YSNaNE,
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output logic [10:0] AddExponentE,
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output logic [10:0] AddExpPostSumE,
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output logic [11:0] AddExp1DenormE, AddExp2DenormE,//KEP used to be [10:0]
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output logic [63:0] AddSumE, AddSumTcE,
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output logic [3:0] AddSelInvE,
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output logic AddCorrSignE,
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output logic AddSignAE,
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output logic AddOpANormE, AddOpBNormE,
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output logic AddInvalidE,
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output logic AddDenormInE,
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output logic AddSwapE
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);
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logic [5:0] ZP_mantissaA;
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logic [5:0] ZP_mantissaB;
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wire ZV_mantissaA;
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wire ZV_mantissaB;
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wire P;
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assign P = ~(FmtE^FOpCtrlE[1]);
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wire [63:0] IntValue;
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wire [11:0] exp1, exp2;
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wire [11:0] exp_diff1, exp_diff2;
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wire [11:0] exp_shift;
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wire [51:0] mantissaA;
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wire [56:0] mantissaA1;
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wire [63:0] mantissaA3;
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wire [51:0] mantissaB;
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wire [56:0] mantissaB1, mantissaB2;
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wire [63:0] mantissaB3;
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wire exp_gt63;
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wire Sticky_out;
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wire sub;
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wire zeroB;
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wire [5:0] align_shift;
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// Test for exceptions and return the "Invalid Operation" and
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// "Denormalized" Input Flags. The "AddSelInvE" is used in
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// the third pipeline stage to select the result. Also, AddOp1NormE
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// and AddOp2NormE are one if FSrcXE and FSrcYE are not zero or denormalized.
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// sub is one if the effective operation is subtaction.
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exception exc1 (.Ztype(AddSelInvE), .Invalid(AddInvalidE), .Denorm(AddDenormInE), .Sub(sub),
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.XSgnE, .YSgnE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE,
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.op_type(FOpCtrlE));
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// Perform Exponent Subtraction (used for alignment). For performance
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// both exponent subtractions are performed in parallel. This was
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// changed to a behavior level to allow the tools to try to optimize
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// the two parallel additions. The input values are zero-extended to 12
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// bits prior to performing the addition.
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assign exp1 = {1'b0, XExpE};
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assign exp2 = {1'b0, YExpE};
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assign exp_diff1 = exp1 - exp2;
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assign exp_diff2 = AddDenormInE ? ({YSgnE, YExpE} - {XSgnE, XExpE}): exp2 - exp1;
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// The second operand (B) should be set to zero, if FOpCtrlE does not
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// specify addition or subtraction
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assign zeroB = FOpCtrlE[1];
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// Swapped operands if zeroB is not one and exp1 < exp2.
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// Swapping causes exp2 to be used for the result exponent.
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// Only the exponent of the larger operand is used to determine
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// the final result.
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assign AddSwapE = exp_diff1[11] & ~zeroB;
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assign AddExponentE = AddSwapE ? YExpE : XExpE;
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assign AddExpPostSumE = AddSwapE ? YExpE : XExpE;
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assign mantissaA = AddSwapE ? YManE[51:0] : XManE[51:0];
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assign mantissaB = AddSwapE ? XManE[51:0] : YManE[51:0];
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assign AddSignAE = AddSwapE ? YSgnE : XSgnE;
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// Leading-Zero Detector. Determine the size of the shift needed for
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// normalization. If sum_corrected is all zeros, the exp_valid is
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// zero; otherwise, it is one.
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// modified to 52 bits to detect leading zeroes on denormalized mantissas
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// lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA);
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// lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB);
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logic [8:0] i;
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logic [8:0] j;
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always_comb begin
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i = 0;
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while (~mantissaA[52-i] && $unsigned(i) <= $unsigned(52)) i = i+1; // search for leading one
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ZP_mantissaA = i;
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end
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always_comb begin
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j = 0;
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while (~mantissaB[52-j] && $unsigned(j) <= $unsigned(52)) j = j+1; // search for leading one
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ZP_mantissaB = j;
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end
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// Denormalized exponents created by subtracting the leading zeroes from the original exponents
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assign AddExp1DenormE = AddSwapE ? (exp1 - {6'b0, ZP_mantissaB}) : (exp1 - {6'b0, ZP_mantissaA}); //KEP extended ZP_mantissa
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assign AddExp2DenormE = AddSwapE ? (exp2 - {6'b0, ZP_mantissaA}) : (exp2 - {6'b0, ZP_mantissaB});
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// Determine the alignment shift and limit it to 63. If any bit from
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// exp_shift[6] to exp_shift[11] is one, then shift is set to all ones.
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assign exp_shift = AddSwapE ? exp_diff2 : exp_diff1;
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assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9]
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| exp_shift[8] | exp_shift[7] | exp_shift[6];
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assign align_shift = exp_shift[5:0] | {6{exp_gt63}}; //KEP used to be all of exp_shift
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// Unpack the 52-bit mantissas to 57-bit numbers of the form.
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// 001.M[51]M[50] ... M[1]M[0]00
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// Unless the number has an exponent of zero, in which case it
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// is unpacked as
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// 000.00 ... 00
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// This effectively flushes denormalized values to zero.
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// The three bits of to the left of the binary point prevent overflow
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// and loss of sign information. The two bits to the right of the
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// original mantissa form the "guard" and "round" bits that are used
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// to round the result.
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assign AddOpANormE = AddSwapE ? YNormE : XNormE;
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assign AddOpBNormE = AddSwapE ? XNormE : YNormE;
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assign mantissaA1 = {2'h0, AddOpANormE, mantissaA[51:0]&{52{AddOpANormE}}, 2'h0};
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assign mantissaB1 = {2'h0, AddOpBNormE, mantissaB[51:0]&{52{AddOpBNormE}}, 2'h0};
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// Perform mantissa alignment using a 57-bit barrel shifter
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// If any of the bits shifted out are one, Sticky_out is set.
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// The size of the barrel shifter could be reduced by two bits
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// by not adding the leading two zeros until after the shift.
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barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift);
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// Place either the sign-extened 32-bit value or the original 64-bit value
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// into IntValue (to be used for integer to floating point conversion)
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// assign IntValue [31:0] = FSrcXE[31:0];
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// assign IntValue [63:32] = FOpCtrlE[0] ? {32{FSrcXE[31]}} : FSrcXE[63:32];
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// If doing an integer to floating point conversion, mantissaA3 is set to
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// IntVal and the prenomalized exponent is set to 1084. Otherwise,
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// mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero,
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// and the exponent value is left unchanged.
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// Under denormalized cases, the exponent before the rounder is set to 1
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// if the normal shift value is 11.
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assign mantissaA3 = AddDenormInE ? ({12'h0, mantissaA}) : {mantissaA1, 7'h0};
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// Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to
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// 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six
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// zeros.
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assign mantissaB3[63:7] = AddDenormInE ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}};
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assign mantissaB3[6] = AddDenormInE ? mantissaB[6] : Sticky_out & ~zeroB;
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assign mantissaB3[5:0] = AddDenormInE ? mantissaB[5:0] : 6'h0;
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// The sign of the result needs to be corrected if the true
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// operation is subtraction and the input operands were swapped.
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assign AddCorrSignE = ~FOpCtrlE[1]&FOpCtrlE[0]&AddSwapE;
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// 64-bit Mantissa Adder/Subtractor
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cla64 add1 (AddSumE, mantissaA3, mantissaB3, sub); //***adder
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// 64-bit Mantissa Subtractor - to get the two's complement of the
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// result when the sign from the adder/subtractor is negative.
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cla_sub64 sub1 (AddSumTcE, mantissaB3, mantissaA3); //***adder
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// Finds normal underflow result to determine whether to round final exponent down
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//***KEP used to be (AddSumE == 16'h0) I am unsure what it's supposed to be
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// assign AddNormOvflowE = (AddDenormInE & (AddSumE == 64'h0) & (AddOpANormE | AddOpBNormE) & ~FOpCtrlE[0]) ? 1'b1 : (AddSumE[63] ? AddSumTcE[52] : AddSumE[52]);
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endmodule // fpadd
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//
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// File name : fpadd
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// Title : Floating-Point Adder/Subtractor
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// project : FPU
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// Library : fpadd
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// Author(s) : James E. Stine, Jr., Brett Mathis
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// Purpose : definition of main unit to floating-point add/sub
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// notes :
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//
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// Copyright Oklahoma State University
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// Copyright AFRL
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//
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// Basic and Denormalized Operations
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//
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// Step 1: Load operands, set flags, and AddConvertM SP to DP
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// Step 2: Check for special inputs ( +/- Infinity, NaN)
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// Step 3: Compare exponents. Swap the operands of exp1 < exp2
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// or of (exp1 = exp2 AND mnt1 < mnt2)
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// Step 4: Shift the mantissa corresponding to the smaller AddExponentM,
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// and extend precision by three bits to the right.
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// Step 5: Add or subtract the mantissas.
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// Step 6: Normalize the result.//
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// Shift left until normalized. Normalized when the value to the
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// left of the binrary point is 1.
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// Step 7: Round the result.//
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// Step 8: Put AddSumM onto output.
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//
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module fpuaddcvt2 (
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input logic [2:0] FrmM, // Rounding mode - specify values
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input logic [2:0] FOpCtrlM, // Function opcode
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input logic FmtM, // Result Precision (0 for double, 1 for single)
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input logic [63:0] AddSumM, AddSumTcM,
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input logic [11:0] AddExp1DenormM, AddExp2DenormM,
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input logic [10:0] AddExponentM, AddExpPostSumM,
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input logic [3:0] AddSelInvM,
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input logic XSgnM, YSgnM,
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input logic [52:0] XManM, YManM,
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input logic [10:0] XExpM, YExpM,
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input logic XNormM, YNormM,
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input logic AddOpANormM, AddOpBNormM,
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input logic AddInvalidM,
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input logic AddDenormInM,
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input logic AddSignAM,
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input logic AddCorrSignM,
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input logic AddSwapM,
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output logic [63:0] FAddResM, // Result of operation
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output logic [4:0] FAddFlgM // IEEE exception flags
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);
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wire AddDenormM; // AddDenormM on input or output
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wire P;
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assign P = ~(FmtM^FOpCtrlM[1]);
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wire [10:0] exp_pre;
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wire [63:0] Result;
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wire [63:0] sum_norm, sum_norm_w_bypass;
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wire [5:0] norm_shift, norm_shift_denorm;
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wire exp_valid;
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wire DenormIO;
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wire [4:0] FlagsIn;
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wire Sticky_out;
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wire sign_corr;
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wire zeroB;
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wire mantissa_comp;
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wire mantissa_comp_sum;
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wire mantissa_comp_sum_tc;
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wire Float1_sum_comp;
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wire Float2_sum_comp;
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wire Float1_sum_tc_comp;
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wire Float2_sum_tc_comp;
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wire normal_underflow;
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wire [63:0] sum_corr;
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logic AddNormOvflowM;
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logic AddOvEnM; // Overflow trap enabled
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logic AddUnEnM; // Underflow trap enabled
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assign AddOvEnM = 1'b1;
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assign AddUnEnM = 1'b1;
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//AddExponentM value pre-rounding with considerations for denormalized
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//cases/conversion cases
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assign exp_pre = AddDenormInM ?
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((norm_shift == 6'b001011) ? 11'b00000000001 : (AddSwapM ? AddExp2DenormM[10:0] : AddExp1DenormM[10:0]))
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: AddExponentM;
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// Finds normal underflow result to determine whether to round final AddExponentM down
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// Comparison between each float and the resulting AddSumM of the primary cla adder/subtractor and cla subtractor
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assign Float1_sum_comp = ~(XManM[51:0] > AddSumM[51:0]);
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assign Float2_sum_comp = ~(YManM[51:0] > AddSumM[51:0]);
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assign Float1_sum_tc_comp = ~(XManM[51:0] > AddSumTcM[51:0]);
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assign Float2_sum_tc_comp = ~(YManM[51:0] > AddSumTcM[51:0]);
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// Determines the correct Float value to compare based on AddSwapM result
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assign mantissa_comp_sum = AddSwapM ? Float2_sum_comp : Float1_sum_comp;
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assign mantissa_comp_sum_tc = AddSwapM ? Float2_sum_tc_comp : Float1_sum_tc_comp;
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// Determines the correct comparison result based on operation and sign of resulting AddSumM
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assign mantissa_comp = (FOpCtrlM[0] ^ AddSumM[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum;
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// If the signs are different and both operands aren't denormalized
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// the normal underflow bit is needed and therefore updated.
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assign normal_underflow = ((XSgnM ^ YSgnM) & (AddOpANormM | AddOpBNormM)) ? mantissa_comp : 1'b0;
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// Determine the correct sign of the result
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assign sign_corr = (AddCorrSignM ^ AddSignAM) ^ AddSumM[63];
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// If the AddSumM is negative, use its two complement instead.
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// This value has to be 64-bits to correctly handle the
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// case 10...00
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assign sum_corr = (AddDenormInM & (AddOpANormM | AddOpBNormM) & ( ( (XSgnM ~^ YSgnM) & FOpCtrlM[0] ) | ((XSgnM ^ YSgnM) & ~FOpCtrlM[0]) ))
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? (AddSumM[63] ? AddSumM : AddSumTcM) : (AddSumM[63] ? AddSumTcM : AddSumM);
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// Finds normal underflow result to determine whether to round final AddExponentM down
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//KEP used to be (AddSumM == 16'h0) not sure what it is supposed to be
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assign AddNormOvflowM = (AddDenormInM & (AddSumM == 64'h0) & (AddOpANormM | AddOpBNormM) & ~FOpCtrlM[0]) ? 1'b1 : (AddSumM[63] ? AddSumTcM[52] : AddSumM[52]);
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// Leading-Zero Detector. Determine the size of the shift needed for
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// normalization. If sum_corrected is all zeros, the exp_valid is
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// zero; otherwise, it is one.
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lz64 lzd1 (norm_shift, exp_valid, sum_corr);
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assign norm_shift_denorm = (AddDenormInM & ( (~AddOpANormM & ~AddOpBNormM) | normal_underflow)) ? (6'h00) : (norm_shift);
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// Barell shifter used for normalization. It takes as inputs the
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// the corrected AddSumM and the amount by which the AddSumM should
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// be right shifted. It outputs the normalized AddSumM.
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barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm);
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assign sum_norm_w_bypass = sum_norm;
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// Round the mantissa to a 52-bit value, with the leading one
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// removed. If the result is a single precision number, the actual
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// mantissa is in the upper 23 bits and the lower 29 bits are zero.
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// At this point, normalization has already been performed, so we know
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// exactly where the rounding point is. The rounding units also
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// handles special cases and set the exception flags.
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// Changed DenormIO -> AddDenormM and FlagsIn -> FAddFlgM in order to
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// help in processor reservation station detection of load/stores. In
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// other words, the processor would like to know ahead of time that
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// if the result is an exception then don't load or store.
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rounder round1 (.Result, .DenormIO, .Flags(FlagsIn), .rm(FrmM), .P, .OvEn(AddOvEnM), .UnEn(AddUnEnM), .exp_valid,
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.sel_inv(AddSelInvM), .Invalid(AddInvalidM), .DenormIn(AddDenormInM), .Asign(sign_corr), .Aexp(exp_pre), .norm_shift, .A(sum_norm_w_bypass),
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.exponent_postsum(AddExpPostSumM), .A_Norm(XNormM), .B_Norm(YNormM), .exp_A_unmodified({XSgnM, XExpM}), .exp_B_unmodified({YSgnM, YExpM}),
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.normal_overflow(AddNormOvflowM), .normal_underflow, .swap(AddSwapM), .op_type(FOpCtrlM), .sum(AddSumM));
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// Store the final result and the exception flags in registers.
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assign FAddResM = Result;
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assign {AddDenormM, FAddFlgM} = {DenormIO, FlagsIn};
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endmodule // fpadd
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