cvw/pipelined/src/uncore
Ross Thompson 5faa88acd5 Increazed fpga clock speed to 35Mhz.
linux boot is much faster.
2022-04-05 15:09:49 -05:00
..
sdc Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
clint.sv Added wave config 2022-04-01 12:44:14 -05:00
gpio.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
plic.sv Added wave config 2022-04-01 12:44:14 -05:00
ram.sv Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
uart.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
uartPC16550D.sv Increazed fpga clock speed to 35Mhz. 2022-04-05 15:09:49 -05:00
uncore.sv Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00