forked from Github_Repos/cvw
114 lines
3.6 KiB
Systemverilog
114 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// ram2p1r1wb
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 15, 2021
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// Modified:
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//
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// Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want
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// to encode to reduce storage), valid, target PC.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module BTBPredictor
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#(parameter int Depth = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallE,
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input logic [`XLEN-1:0] LookUpPC,
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output logic [`XLEN-1:0] TargetPC,
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output logic [4:0] InstrClass,
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output logic Valid,
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// update
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input logic UpdateEN,
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input logic [`XLEN-1:0] UpdatePC,
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input logic [`XLEN-1:0] UpdateTarget,
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input logic [4:0] UpdateInstrClass,
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input logic UpdateInvalid
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);
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localparam TotalDepth = 2 ** Depth;
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logic [TotalDepth-1:0] ValidBits;
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logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
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logic UpdateENQ;
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// hashing function for indexing the PC
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// We have Depth bits to index, but XLEN bits as the input.
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// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
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// using compressed instructions. XOR bit 1 with the MSB of index.
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assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
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assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};
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flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.d(UpdatePCIndex),
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.q(UpdatePCIndexQ));
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// The valid bit must be resetable.
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always_ff @ (posedge clk) begin
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if (reset) begin
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ValidBits <= #1 {TotalDepth{1'b0}};
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end else
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if (UpdateENQ) begin
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ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid;
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end
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end
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assign Valid = ValidBits[LookUpPCIndexQ];
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flopenr #(1) UpdateENReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(UpdateEN),
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.q(UpdateENQ));
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flopenr #(Depth) LookupPCIndexReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(LookUpPCIndex),
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.q(LookUpPCIndexQ));
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// the BTB contains the target address.
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// Another optimization may be using a PC relative address.
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// *** need to add forwarding.
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// *** optimize for byte write enables
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ram2p1r1wb #(Depth, `XLEN+5) memory(.clk(clk),
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.reset(reset),
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.ra1(LookUpPCIndex),
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.rd1({{InstrClass, TargetPC}}),
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.ren1(~StallF),
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.wa2(UpdatePCIndex),
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.wd2({UpdateInstrClass, UpdateTarget}),
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.wen2(UpdateEN),
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.bwe2({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
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endmodule
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