forked from Github_Repos/cvw
84 lines
4.1 KiB
Systemverilog
84 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// pmachecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and identifies attributes of
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// the memory region accessed.
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// Can report illegal accesses to the trap unit and cause a fault.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pmachecker (
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// input logic clk, reset, // *** unused in this module and all sub modules.
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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// input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
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output logic Cacheable, Idempotent, AtomicAllowed,
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output logic PMASquashBusAccess,
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output logic [5:0] HSELRegions,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAccessFaultM
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);
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// logic BootTim, Tim, CLINT, GPIO, UART, PLIC;
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logic PMAAccessFault;
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logic AccessRW, AccessRWX, AccessRX;
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// Determine what type of access is being made
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assign AccessRW = ReadAccessM | WriteAccessM;
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assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
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assign AccessRX = ReadAccessM | ExecuteAccessF;
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// Determine which region of physical memory (if any) is being accessed
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// *** linux tests fail early when Access is anything other than 1b1
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pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]);
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pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]);
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pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), HSELRegions[3]);
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pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]);
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pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]);
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pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]);
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// Only RAM memory regions are cacheable
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assign Cacheable = HSELRegions[5] | HSELRegions[4];
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assign Idempotent = HSELRegions[4];
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assign AtomicAllowed = HSELRegions[4];
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/*ExecuteAccessF | ReadAccessM | WriteAccessM; */
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// Swizzle region bits
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//assign HSELRegions = {BootTim, Tim, CLINT, GPIO, UART, PLIC};
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// Detect access faults
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assign PMAAccessFault = ~|HSELRegions;
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assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
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assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
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assign PMASquashBusAccess = PMAAccessFault && AccessRWX;
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endmodule
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