forked from Github_Repos/cvw
74 lines
2.6 KiB
Systemverilog
Executable File
74 lines
2.6 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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// shifters.sv
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//
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// Written: James.Stine@okstate.edu 1 February 2021
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// Modified:
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//
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// Purpose: Integer Divide instructions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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module shift_right #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] A,
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input logic [$clog2(WIDTH)-1:0] Shift,
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output logic [WIDTH-1:0] Z);
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logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
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logic sign;
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genvar i;
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assign stage[0] = A;
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generate
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for (i=0;i<$clog2(WIDTH);i=i+1)
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begin : genbit
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mux2 #(WIDTH) mux_inst (stage[i],
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{{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]},
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Shift[$clog2(WIDTH)-i-1],
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stage[i+1]);
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end
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endgenerate
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assign Z = stage[$clog2(WIDTH)];
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endmodule // shift_right
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module shift_left #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] A,
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input logic [$clog2(WIDTH)-1:0] Shift,
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output logic [WIDTH-1:0] Z);
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logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
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genvar i;
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assign stage[0] = A;
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generate
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for (i=0;i<$clog2(WIDTH);i=i+1)
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begin : genbit
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mux2 #(WIDTH) mux_inst (stage[i],
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{stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}},
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Shift[$clog2(WIDTH)-i-1],
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stage[i+1]);
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end
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endgenerate
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assign Z = stage[$clog2(WIDTH)];
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endmodule // shift_left
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