forked from Github_Repos/cvw
106 lines
3.9 KiB
Systemverilog
106 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: David Harris
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// Modified: 11 September 2021
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//
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// Purpose: Recurrence-based SRT Division and Square Root
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// Bit counts:
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// Inputs are originally normalized floating point numbers with NF fractional bits and a leading 1 integer bit
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// x is right shifted by up to 2 to be in the range of 1/4 <= x < 1/2 for divide, 1/4 <= x < 1 for sqrt
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// Hence, x now has NF+2 fractional bits and 0 integer bits
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// d is right shifted by 1 to be in the range of 1/2 <= d < 1. It thus has NF+1 fractional bits and 0 integer bits
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// q is eventually in the range of 1/4 < q < 1 and hence needs NF+2 bits to keep NF bits when normalized, plus some*** more bits for rounding
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// The partial
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/*
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module fpudivsqrtrecurcore (
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input logic clk,
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input logic reset,
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input logic start, // start a computation
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input logic busy, // computation running
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input logic fmt, // precision 1 = double 0 = single
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input logic [`NF+1:0] x, // in range 1/4 <= x < 1/2 for divide, 1/4 <=x < 1 for sqrt
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input logic [`NF+1:0] din, // in range 1/2 <= d < 1 for divide
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input logic FDiv, FSqrt, // *** not yet used
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output logic [`FLEN-1:0] FDivSqrtRecurRes // result
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);
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assign FDivSqrtRecurRes = 0;
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logic [***] d, ws, wsout, wsnext, wc, wcout, wcnext;
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logic [1:0] q; // 00 = 0, 01 = 1, 10 = -1
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// Radix-2 SRT Division
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// registers for divisor and partial remainder
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flopen #(NF+1) dreg(clk, start, din, d);
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mux2 #(NF+1) wsmux(wsout, x, start, wsnext);
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flopen #(NF+1) wsreg(clk, busy, wsnext, ws);
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mux2 #(NF+1) wcmux(wcout, 0, start, wcnext);
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flopen #(NF+1) wcreg(clk, busy, wcnext, wc);
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// quotient selection
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qsel qsel(ws[***4bits], wc[***], q);
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// partial remainder update
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always_comb begin // select -d * q to add to partial remainder
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if (q[1]) dq = d;
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else if (q[0]) dq = ~d;
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else dq = 0;
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end
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csa #(***) csa(ws, wc, dq, q[1], wsout, wcout);
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endmodule
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*/
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/*
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module csa #(parameter N=4) (
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input logic [N-1:0] sin, cin, ain,
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input logic carry,
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output logic [N-1:0] sum, cout
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);
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logic [N-1:0] c;
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assign c = {cin[N-2:0], carry}; // shift carries left and inject optional 1 into lsb
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assign sum = sin ^ ain ^ c;
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assign cout = sin & ain | sin & c | ain & c;
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endmodule
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*/
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module qsel( // radix 2 SRT division quotient selection
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input logic [3:0] wc, ws,
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output logic [1:0] q
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);
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endmodule
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