forked from Github_Repos/cvw
112 lines
5.1 KiB
Systemverilog
112 lines
5.1 KiB
Systemverilog
///////////////////////////////////////////
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// btb.sv
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//
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// Written: Ross Thomposn ross1728@gmail.com
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// Created: February 15, 2021
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// Modified: 24 January 2023
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//
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// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
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// It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
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//
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// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module btb
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#(parameter int Depth = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallM, FlushD, FlushM,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
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output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
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output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
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output logic PredValidF, // BTB's guess is valid
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// update
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input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong
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input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
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input logic [3:0] InstrClassE // Instruction class to insert into btb
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);
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localparam TotalDepth = 2 ** Depth;
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logic [TotalDepth-1:0] ValidBits;
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logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
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logic [`XLEN-1:0] ResetPC;
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logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
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logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
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logic [`XLEN+3:0] TableBTBPredictionF;
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logic [`XLEN-1:0] PredPCD;
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logic [3:0] PredInstrClassD; // *** copy of reg outside module
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logic UpdateEn;
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logic TablePredValidF;
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// hashing function for indexing the PC
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// We have Depth bits to index, but XLEN bits as the input.
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// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
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// using compressed instructions. XOR bit 1 with the MSB of index.
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assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
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assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
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assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
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// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
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// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
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// While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
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// For now it is optimal to leave it here.
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assign ResetPC = `RESET_VECTOR;
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assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
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assign MatchF = PCNextFIndex == PCFIndex;
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assign MatchD = PCNextFIndex == PCDIndex;
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assign MatchE = PCNextFIndex == PCEIndex;
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assign MatchNextX = MatchF | MatchD | MatchE;
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flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
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assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
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MatchD ? {PredInstrClassD, PredPCD} :
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{InstrClassE, IEUAdrE} ;
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flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
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assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
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always_ff @ (posedge clk) begin
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if (reset) begin
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ValidBits <= #1 {TotalDepth{1'b0}};
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end else if ((UpdateEn) & ~StallM & ~FlushM) begin
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ValidBits[PCEIndex] <= #1 |InstrClassE;
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end
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if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
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end
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assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
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assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
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// An optimization may be using a PC relative address.
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ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
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.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
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flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
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endmodule
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