cvw/pipelined/src/fpu
2022-12-04 00:01:58 +00:00
..
fdivsqrt Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 2022-12-04 00:01:58 +00:00
fma Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
postproc FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
fclassify.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fcmp.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fctrl.sv Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
fcvt.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fhazard.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fpu.sv Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
fregfile.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fsgninj.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
normshift.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpack.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpackinput.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00