cvw/pipelined/src/generic/flop
2022-01-13 22:21:43 -06:00
..
flop.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopen.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopenl.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopenr.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopenrc.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopens.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
flopr.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
floprc.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
simpleram.sv Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
synchronizer.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00