forked from Github_Repos/cvw
110 lines
3.9 KiB
Systemverilog
110 lines
3.9 KiB
Systemverilog
/* parameter cvw_t P = '{
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PA_BITS : PA_BITS,
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XLEN: XLEN,
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AHBW: AHBW,
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MISA: MISA,
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BUS_SUPPORTED: BUS_SUPPORTED,
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ZICSR_SUPPORTED: ZICSR_SUPPORTED,
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M_SUPPORTED: M_SUPPORTED,
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ZMMUL_SUPPORTED: ZMMUL_SUPPORTED,
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F_SUPPORTED: F_SUPPORTED,
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PMP_ENTRIES: PMP_ENTRIES,
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LLEN: LLEN,
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FPGA: FPGA,
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QEMU: QEMU,
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VPN_SEGMENT_BITS: VPN_SEGMENT_BITS,
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FLEN: FLEN
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}, */
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// Populate parameter structure with values specific to the current configuration
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parameter cvw_t P = '{
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FPGA : FPGA,
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QEMU : QEMU,
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XLEN : XLEN,
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IEEE754 : IEEE754,
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MISA : MISA,
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AHBW : AHBW,
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ZICSR_SUPPORTED : ZICSR_SUPPORTED,
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ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
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COUNTERS : COUNTERS,
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ZICOUNTERS_SUPPORTED : ZICOUNTERS_SUPPORTED,
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ZFH_SUPPORTED : ZFH_SUPPORTED,
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SSTC_SUPPORTED : SSTC_SUPPORTED,
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VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
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VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
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BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
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SVADU_SUPPORTED : SVADU_SUPPORTED,
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ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
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BUS_SUPPORTED : BUS_SUPPORTED,
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DCACHE_SUPPORTED : DCACHE_SUPPORTED,
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ICACHE_SUPPORTED : ICACHE_SUPPORTED,
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ITLB_ENTRIES : ITLB_ENTRIES,
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DTLB_ENTRIES : DTLB_ENTRIES,
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DCACHE_NUMWAYS : DCACHE_NUMWAYS,
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DCACHE_WAYSIZEINBYTES : DCACHE_WAYSIZEINBYTES,
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DCACHE_LINELENINBITS : DCACHE_LINELENINBITS,
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ICACHE_NUMWAYS : ICACHE_NUMWAYS,
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ICACHE_WAYSIZEINBYTES : ICACHE_WAYSIZEINBYTES,
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ICACHE_LINELENINBITS : ICACHE_LINELENINBITS,
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IDIV_BITSPERCYCLE : IDIV_BITSPERCYCLE,
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IDIV_ON_FPU : IDIV_ON_FPU,
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PMP_ENTRIES : PMP_ENTRIES,
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RESET_VECTOR : RESET_VECTOR,
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WFI_TIMEOUT_BIT : WFI_TIMEOUT_BIT,
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DTIM_SUPPORTED : DTIM_SUPPORTED,
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DTIM_BASE : DTIM_BASE,
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DTIM_RANGE : DTIM_RANGE,
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IROM_SUPPORTED : IROM_SUPPORTED,
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IROM_BASE : IROM_BASE,
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IROM_RANGE : IROM_RANGE,
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BOOTROM_SUPPORTED : BOOTROM_SUPPORTED,
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BOOTROM_BASE : BOOTROM_BASE,
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BOOTROM_RANGE : BOOTROM_RANGE,
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UNCORE_RAM_SUPPORTED : UNCORE_RAM_SUPPORTED,
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UNCORE_RAM_BASE : UNCORE_RAM_BASE,
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UNCORE_RAM_RANGE : UNCORE_RAM_RANGE,
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EXT_MEM_SUPPORTED : EXT_MEM_SUPPORTED,
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EXT_MEM_BASE : EXT_MEM_BASE,
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EXT_MEM_RANGE : EXT_MEM_RANGE,
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CLINT_SUPPORTED : CLINT_SUPPORTED,
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CLINT_BASE : CLINT_BASE,
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CLINT_RANGE : CLINT_RANGE,
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GPIO_SUPPORTED : GPIO_SUPPORTED,
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GPIO_BASE : GPIO_BASE,
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GPIO_RANGE : GPIO_RANGE,
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UART_SUPPORTED : UART_SUPPORTED,
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UART_BASE : UART_BASE,
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UART_RANGE : UART_RANGE,
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PLIC_SUPPORTED : PLIC_SUPPORTED,
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PLIC_BASE : PLIC_BASE,
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PLIC_RANGE : PLIC_RANGE,
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SDC_SUPPORTED : SDC_SUPPORTED,
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SDC_BASE : SDC_BASE,
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SDC_RANGE : SDC_RANGE,
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AHBW : AHBW,
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GPIO_LOOPBACK_TEST : GPIO_LOOPBACK_TEST,
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UART_PRESCALE : UART_PRESCALE ,
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PLIC_NUM_SRC : PLIC_NUM_SRC,
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PLIC_NUM_SRC_LT_32 : PLIC_NUM_SRC_LT_32,
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PLIC_GPIO_ID : PLIC_GPIO_ID,
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PLIC_UART_ID : PLIC_UART_ID,
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BPRED_SUPPORTED : BPRED_SUPPORTED,
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//parameter : BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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BPRED_SIZE : BPRED_SIZE,
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BTB_SIZE : BTB_SIZE,
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RADIX : RADIX,
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DIVCOPIES : DIVCOPIES,
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ZBA_SUPPORTED : ZBA_SUPPORTED,
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ZBB_SUPPORTED : ZBB_SUPPORTED,
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ZBC_SUPPORTED : ZBC_SUPPORTED,
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ZBS_SUPPORTED : ZBS_SUPPORTED,
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USE_SRAM : USE_SRAM,
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M_SUPPORTED :M_SUPPORTED,
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F_SUPPORTED :F_SUPPORTED,
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LLEN :LLEN,
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FLEN :FLEN,
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VPN_SEGMENT_BITS :VPN_SEGMENT_BITS,
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PA_BITS : PA_BITS
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};
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