forked from Github_Repos/cvw
66 lines
2.1 KiB
Systemverilog
66 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtuotfc4.sv
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//
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// Written: me@KatherineParry.com, cturek@hmc.edu
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// Modified:7/14/2022
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//
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// Purpose: Radix 4 unified on-the-fly converter
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtuotfc4(
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input logic [3:0] udigit,
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input logic [`DIVb:0] U, UM,
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input logic [`DIVb:0] C,
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output logic [`DIVb:0] UNext, UMNext
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);
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// The on-the-fly converter transfers the square root
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// bits to the quotient as they come.
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// Use this otfc for division and square root.
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logic [`DIVb:0] K1, K2, K3;
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assign K1 = (C&~(C << 1)); // K
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assign K2 = ((C << 1)&~(C << 2)); // 2K
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assign K3 = (C & ~(C << 2)); // 3K
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always_comb begin
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if (udigit[3]) begin // +2
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UNext = U | K2;
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UMNext = U | K1;
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end else if (udigit[2]) begin // +1
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UNext = U | K1;
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UMNext = U;
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end else if (udigit[1]) begin // -1
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UNext = UM | K3;
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UMNext = UM | K2;
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end else if (udigit[0]) begin // -2
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UNext = UM | K2;
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UMNext = UM | K1;
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end else begin // 0
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UNext = U;
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UMNext = UM | K3;
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end
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end
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endmodule
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