Alec Vercruysse cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. ... This test basically triggers an i$ miss during a d$ (hit) store operation. It requires some tricky timing (e.g. a flushD right before the relevant store). I use a script to generate the test.		2023-04-19 01:34:01 -07:00
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csrwrites.S	Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf	2023-04-07 21:11:01 -07:00
dcache1.py	Cover CacheWay edge case: CacheDataMem we=1 while ce=0.	2023-04-19 01:34:01 -07:00
dcache1.S	Cover CacheWay edge case: CacheDataMem we=1 while ce=0.	2023-04-19 01:34:01 -07:00
ebu.S	Start of EBU coverage tests	2023-03-24 08:12:02 -07:00
fpu.S	Added multiple tests to increase FPU coverage	2023-04-14 14:41:05 -05:00
ieu.S	Fixed WALLY-init-lib to return correctly even from traps from compressed instructions	2023-04-07 20:24:33 -07:00
ifu.S	Fixed WALLY-init-lib to return correctly even from traps from compressed instructions	2023-04-07 20:24:33 -07:00
ifuCamlineWrite.S	Increase of TLB coverage in IFU	2023-04-17 18:35:03 -07:00
lsu.S	add back K. Box and M. Cook Lsu test	2023-04-13 17:50:18 -07:00
Makefile	Started adding fpu fctrl tests	2023-03-28 21:13:25 -07:00
pmp.S	Create new pmp tests	2023-04-09 16:29:57 -07:00
priv.S	Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc	2023-04-15 23:13:39 -07:00
tlbKP.S	update tests.vh, add tlbKP to load all lines of tlb	2023-04-13 15:13:55 -07:00
vm64check.S	Added vm64check tests to cover IMMU vm64	2023-04-07 21:14:52 -07:00
WALLY-init-lib.h	Fixed exception handling to handle ecalls properly	2023-04-13 09:23:32 -07:00