forked from Github_Repos/cvw
50 lines
2.2 KiB
Systemverilog
50 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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// priorityonehot.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
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// Modified: Teo Ene 15 Apr 2021:
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// Temporarily removed paramterized priority encoder for non-parameterized one
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// To get synthesis working quickly
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// Kmacsaigoren@hmc.edu 28 May 2021:
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// Added working version of parameterized priority encoder.
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// David_Harris@Hmc.edu switched to one-hot output
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//
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// Purpose: Priority circuit producing a 1 in the output in the column where
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// the least significant 1 appears in the input.
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//
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// Example: msb lsb
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// in 01011101010100000
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// out 00000000000100000
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module priorityonehot #(parameter N = 8) (
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input logic [N-1:0] a,
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output logic [N-1:0] y
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);
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genvar i;
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assign y[0] = a[0];
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for (i=1; i<N; i++) begin:poh
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assign y[i] = a[i] & ~|a[i-1:0];
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end
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endmodule
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