Alessandro Maiuolo 5a82898649 Added NumZeroE, AZeroM, and BZeroM		2022-12-18 20:02:40 -08:00
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fdivsqrt.sv	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
fdivsqrtfgen2.sv	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
fdivsqrtfgen4.sv	renamed u to udigit to avoid conflict with U	2022-09-20 19:29:23 -07:00
fdivsqrtfsm.sv	Added mux for integer special case, renamed signals to match pipelined stage	2022-12-16 18:43:49 +00:00
fdivsqrtiter.sv	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
fdivsqrtpostproc.sv	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
fdivsqrtpreproc.sv	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
fdivsqrtqsel2.sv	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
fdivsqrtqsel4.sv	New fdivsqrtqsel4cmp module based on comparators rather than table lookup	2022-10-09 04:47:44 -07:00
fdivsqrtqsel4cmp.sv	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
fdivsqrtstage2.sv	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
fdivsqrtstage4.sv	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
fdivsqrtuotfc2.sv	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
fdivsqrtuotfc4.sv	renamed u to udigit to avoid conflict with U	2022-09-20 19:29:23 -07:00