forked from Github_Repos/cvw
82 lines
3.4 KiB
Systemverilog
82 lines
3.4 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfsm.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: divsqrt state machine for multi-cycle operations
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfsm(
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input logic clk, reset,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic FDivStartE, IDivStartE,
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input logic XsE, WZeroE,
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input logic SqrtE,
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input logic StallM, FlushE,
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input logic IntDivE,
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input logic ISpecialCaseE,
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input logic [`DURLEN-1:0] cycles,
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output logic IFDivStartE,
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output logic FDivBusyE, FDivDoneE,
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output logic SpecialCaseM
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);
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
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statetype state;
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logic SpecialCaseE, FSpecialCaseE;
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logic [`DURLEN-1:0] step;
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// FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
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assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
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assign FDivDoneE = (state == DONE);
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assign FDivBusyE = (state == BUSY) | IFDivStartE;
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// terminate immediately on special cases
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assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
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if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
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else assign SpecialCaseE = FSpecialCaseE;
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flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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always_ff @(posedge clk) begin
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if (reset | FlushE) begin
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state <= #1 IDLE;
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end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
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// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
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step <= cycles;
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if (SpecialCaseE) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (state == BUSY) begin
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if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual
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step <= step - 1;
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end else if (state == DONE) begin
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if (StallM) state <= #1 DONE;
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else state <= #1 IDLE;
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end
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end
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endmodule |