forked from Github_Repos/cvw
521 lines
22 KiB
Systemverilog
521 lines
22 KiB
Systemverilog
///////////////////////////////////////////
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// testbench-linux.sv
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//
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// Written: nboorstin@g.hmc.edu 2021
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// Modified:
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//
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// Purpose: Testbench for buildroot or busybear linux
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// When letting Wally go for it, let wally generate own interrupts
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///////////////////////////////////////////
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`include "wally-config.vh"
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`define DEBUG_TRACE 2
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// Debug Levels
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// 0: don't check against QEMU
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// 1: print disagreements with QEMU, but only halt on PCW disagreements
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// 2: halt on any disagreement with QEMU except CSRs
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// 3: halt on all disagreements with QEMU
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// 4: print memory accesses whenever they happen
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// 5: print everything
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6300000; // # of instructions at which to turn on waves in graphical sim
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string ProgramAddrMapFile, ProgramLabelMapFile;
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////// DUT /////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset;
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logic [`AHBW-1:0] readDataExpected;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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wallypipelinedsoc dut(.*);
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////// Signals & Shared Macros ///////////////////////////
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//////////////////////// AKA stuff that comes first ///////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Sorry if these have gotten decontextualized.
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// Verilog expects them to be defined before they are used.
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// -------------------
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// Signal Declarations
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// -------------------
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// Testbench Core
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integer warningCount = 0;
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integer errorCount = 0;
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integer MIPexpected;
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// P, Instr Checking
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logic [`XLEN-1:0] PCW;
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integer data_file_all;
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string name;
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// Write Back stage signals needed for trace compare, but don't actually
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// exist in CPU.
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logic [`XLEN-1:0] MemAdrW, WriteDataW;
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// Write Back trace signals
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logic checkInstrW;
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//integer RegAdr;
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integer fault;
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logic TrapW;
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// Signals used to parse the trace file.
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logic checkInstrM;
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integer matchCount;
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string line;
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logic [`XLEN-1:0] ExpectedPCM;
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logic [31:0] ExpectedInstrM;
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string textM;
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string token;
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string ExpectedTokens [31:0];
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integer index;
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integer StartIndex, EndIndex;
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integer TokenIndex;
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integer MarkerIndex;
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integer NumCSRM;
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// Memory stage expected values from trace
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string RegWriteM;
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integer ExpectedRegAdrM;
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logic [`XLEN-1:0] ExpectedRegValueM;
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string MemOpM;
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logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
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string ExpectedCSRArrayM[10:0];
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logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
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// Write back stage expected values from trace
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logic [`XLEN-1:0] ExpectedPCW;
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logic [31:0] ExpectedInstrW;
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string textW;
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string RegWriteW;
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integer ExpectedRegAdrW;
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logic [`XLEN-1:0] ExpectedRegValueW;
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string MemOpW;
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logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
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integer NumCSRW;
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string ExpectedCSRArrayW[10:0];
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logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
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logic [`XLEN-1:0] ExpectedIntType;
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logic forcedInterrupt;
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integer NumCSRMIndex;
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integer NumCSRWIndex;
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integer NumCSRPostWIndex;
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logic [`XLEN-1:0] InstrCountW;
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integer RequestDelayedMIP;
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// ------
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// Macros
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// ------
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`define CSRwarn(CSR) \
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begin \
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
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$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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if(`DEBUG_TRACE >= 3) fault = 1; \
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end \
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end
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`define checkEQ(NAME, VAL, EXPECTED) \
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if(VAL != EXPECTED) begin \
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$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
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if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \
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end
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initial begin
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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InstrCountW = '0;
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force dut.hart.priv.SwIntM = 0;
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force dut.hart.priv.TimerIntM = 0;
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force dut.hart.priv.ExtIntM = 0;
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end
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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// Additonal W stage registers
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flopenrc #(`XLEN) MemAdrWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.WriteDataM, WriteDataW);
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flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW);
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// Because qemu does not match exactly to wally it is necessary to read the the
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// trace in the memory stage and detect if anything in wally must be overwritten.
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// This includes mtimer, interrupts, and various bits in mstatus and xtval.
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// then on the next posedge the expected state is registered.
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// on the next falling edge the expected state is compared to the wally state.
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// step 0: read the expected state
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always @(negedge clk) begin
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// always check PC, instruction bits
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if (checkInstrM) begin
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// read 1 line of the trace file
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matchCount = $fgets(line, data_file_all);
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if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line);
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// extract PC, Instr
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matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM);
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//$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM);
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// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work.
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// strtok was the best idea but it cannot be used correctly as system verilog does not have null
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// terminated strings.
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// Just going to do this char by char.
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StartIndex = 0;
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TokenIndex = 0;
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//$display("len = %d", line.len());
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for(index = 0; index < line.len(); index++) begin
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//$display("char = %s", line[index]);
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if (line[index] == " " || line[index] == "\n") begin
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EndIndex = index;
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ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1);
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//$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1));
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StartIndex = EndIndex + 1;
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TokenIndex++;
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end
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end
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MarkerIndex = 3;
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NumCSRM = 0;
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MemOpM = "";
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RegWriteM = "";
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#2;
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while(TokenIndex > MarkerIndex) begin
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// parse the GPR
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if (ExpectedTokens[MarkerIndex] == "GPR") begin
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RegWriteM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
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MarkerIndex += 3;
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// parse memory address, read data, and/or write data
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end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
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MemOpM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
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MarkerIndex += 4;
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// parse CSRs, because there are 1 or more CSRs after the CSR token
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// we check if the CSR token or the number of CSRs is greater than 0.
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// if so then we want to parse for a CSR.
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end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
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if(ExpectedTokens[MarkerIndex] == "CSR") begin
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// all additional CSR's won't have this token.
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MarkerIndex++;
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end
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matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
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MarkerIndex += 2;
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// match MIP to QEMU's because interrupts are imprecise
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if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin
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$display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]);
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$display("%tn: ExpectedPCM = %x",$time,ExpectedPCM);
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// if PC does not equal MEPC, request delayed MIP is True
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if(ExpectedPCM != ExpectedCSRArrayM[7]) begin
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RequestDelayedMIP = 1;
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end else begin
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$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
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MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
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force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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end
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end
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NumCSRM++;
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end
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end
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// override on special conditions
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
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end
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if(textM.substr(0,5) == "rdtime") begin
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
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end
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end
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end
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// step 1: register expected state into the write back stage.
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always @(posedge clk) begin
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if (reset) begin
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ExpectedPCW <= '0;
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ExpectedInstrW <= '0;
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textW <= "";
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RegWriteW <= "";
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ExpectedRegAdrW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedMemAdrW <= '0;
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MemOpW <= "";
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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end else if(~dut.hart.StallW) begin
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if(dut.hart.FlushW) begin
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ExpectedPCW <= '0;
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ExpectedInstrW <= '0;
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textW <= "";
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RegWriteW <= "";
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ExpectedRegAdrW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedMemAdrW <= '0;
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MemOpW <= "";
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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end else begin
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ExpectedPCW <= ExpectedPCM;
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ExpectedInstrW <= ExpectedInstrM;
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textW <= textM;
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RegWriteW <= RegWriteM;
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ExpectedRegAdrW <= ExpectedRegAdrM;
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ExpectedRegValueW <= ExpectedRegValueM;
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ExpectedMemAdrW <= ExpectedMemAdrM;
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MemOpW <= MemOpM;
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ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
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ExpectedMemReadDataW <= ExpectedMemReadDataM;
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NumCSRW <= NumCSRM;
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for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin
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ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
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ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
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end
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end
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#1;
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// override on special conditions
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if(~dut.hart.StallW) begin
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if(textW.substr(0,5) == "rdtime") begin
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//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
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release dut.uncore.clint.clint.MTIME;
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end
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
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release dut.hart.ieu.dp.ReadDataM;
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end
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end
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end
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end
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// step2: make all checks in the write back stage.
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always @(negedge clk) begin
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if(RequestDelayedMIP) begin
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$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
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MIPexpected = ExpectedCSRArrayValueW[NumCSRM];
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force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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RequestDelayedMIP = 0;
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end
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// always check PC, instruction bits
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if (checkInstrW) begin
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InstrCountW += 1;
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// turn on waves at certain point
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if (InstrCountW == waveOnICount) $stop;
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// print progress message
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if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
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fault = 0;
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if (`DEBUG_TRACE >= 1) begin
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`checkEQ("PCW",PCW,ExpectedPCW)
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`checkEQ("InstrW",dut.hart.ifu.InstrW,ExpectedInstrW)
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`checkEQ("Instr Count",dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW,InstrCountW)
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#2; // delay 2 ns.
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if(`DEBUG_TRACE >= 5) begin
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$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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end
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if (RegWriteW == "GPR") begin
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`checkEQ("Reg Write Address",dut.hart.ieu.dp.regf.a3,ExpectedRegAdrW)
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$sformat(name,"RF[%02d]",ExpectedRegAdrW);
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`checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
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end
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if (MemOpW.substr(0,2) == "Mem") begin
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if(`DEBUG_TRACE >= 4) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
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`checkEQ("MemAdrW",MemAdrW,ExpectedMemAdrW)
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if(MemOpW == "MemR" || MemOpW == "MemRW") begin
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if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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`checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
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end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
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if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
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`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
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end
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end
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// check csr
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for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
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"mstatus": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
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"mtvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
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"mip": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
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"mie": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
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"mideleg":`CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
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"medeleg": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
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"mepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
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"mtval": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
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"sepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
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"scause": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
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"stvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
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"stval": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
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endcase
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end
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if (fault == 1) begin
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errorCount +=1;
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$display("processed %0d instructions with %0d warnings", InstrCountW, warningCount);
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$stop;
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end
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end // if (`DEBUG_TRACE >= 1)
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end // if (checkInstrW)
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end // always @ (negedge clk)
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// track the current function
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FunctionName FunctionName(.reset(reset),
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.clk(clk),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////////////// Testbench Core ///////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// --------------
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// Initialization
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// --------------
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// initial loading of memories
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initial begin
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$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
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$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
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ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
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end
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// -------
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// Running
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// -------
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////// Miscellaneous ///////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Instr Opcode Tracking
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// For waveview convenience
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.icache.FinalInstrRawF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// ------------------
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// Address Translator
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// ------------------
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/**
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* Walk the page table stored in dtim according to sv39 logic and translate a
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* virtual address to a physical address.
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*
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* See section 4.3.2 of the RISC-V Privileged specification for a full
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* explanation of the below algorithm.
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*/
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logic SvMode, PTE_R, PTE_X;
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logic [`XLEN-1:0] SATP, PTE;
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logic [55:0] BaseAdr, PAdr;
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logic [8:0] VPN [2:0];
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logic [11:0] Offset;
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function logic [`XLEN-1:0] adrTranslator(
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input logic [`XLEN-1:0] adrIn);
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begin
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int i;
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// Grab the SATP register from privileged unit
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SATP = dut.hart.priv.csr.SATP_REGW;
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// Split the virtual address into page number segments and offset
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VPN[2] = adrIn[38:30];
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VPN[1] = adrIn[29:21];
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VPN[0] = adrIn[20:12];
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Offset = adrIn[11:0];
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// We do not support sv48; only sv39
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SvMode = SATP[63];
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// Only perform translation if translation is on and the processor is not
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// in machine mode
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if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin
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BaseAdr = SATP[43:0] << 12;
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for (i = 2; i >= 0; i--) begin
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PAdr = BaseAdr + (VPN[i] << 3);
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// dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
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// by 3 (the PTE size) to get the requested 64-bit PTE.
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PTE = dut.uncore.dtim.RAM[PAdr >> 3];
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PTE_R = PTE[1];
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PTE_X = PTE[3];
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if (PTE_R || PTE_X) begin
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// Leaf page found
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break;
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end else begin
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// Go to next level of table
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BaseAdr = PTE[53:10] << 12;
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end
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end
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// Determine which parts of the PTE page number to use based on the
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// level of the page table we reached.
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if (i == 2) begin
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// Gigapage
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assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset};
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end else if (i == 1) begin
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// Megapage
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assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset};
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end else begin
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// Kilopage
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assign adrTranslator = {8'b0, PTE[53:10], Offset};
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end
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end else begin
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// Direct translation if address translation is not on
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assign adrTranslator = adrIn;
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end
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end
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endfunction
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endmodule
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