forked from Github_Repos/cvw
162 lines
3.9 KiB
ArmAsm
162 lines
3.9 KiB
ArmAsm
// -----------
|
|
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
|
|
// version : 0.5.1
|
|
// timestamp : Mon Aug 2 08:58:53 2021 GMT
|
|
// usage : riscv_ctg \
|
|
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
|
|
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
|
|
// --base-isa rv32e \
|
|
// --randomize
|
|
// -----------
|
|
//
|
|
// -----------
|
|
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
|
// SPDX-License-Identifier: BSD-3-Clause
|
|
// -----------
|
|
//
|
|
// This assembly file tests the lhu instruction of the RISC-V E extension for the lhu-align covergroup.
|
|
//
|
|
#define RVTEST_E
|
|
#include "model_test.h"
|
|
#include "arch_test.h"
|
|
RVTEST_ISA("RV32E")
|
|
|
|
.section .text.init
|
|
.globl rvtest_entry_point
|
|
rvtest_entry_point:
|
|
RVMODEL_BOOT
|
|
RVTEST_CODE_BEGIN
|
|
|
|
#ifdef TEST_CASE_1
|
|
|
|
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lhu-align)
|
|
|
|
RVTEST_SIGBASE( x7,signature_x7_1)
|
|
|
|
inst_0:
|
|
// rs1 != rd, rs1==x15, rd==x9, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
|
|
// opcode:lhu op1:x15; dest:x9; immval:-0x4; align:0
|
|
TEST_LOAD(x7,x1,0,x15,x9,-0x4,0,lhu,0)
|
|
|
|
inst_1:
|
|
// rs1 == rd, rs1==x3, rd==x3, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
|
|
// opcode:lhu op1:x3; dest:x3; immval:0x5; align:0
|
|
TEST_LOAD(x7,x1,0,x3,x3,0x5,4,lhu,0)
|
|
|
|
inst_2:
|
|
// rs1==x13, rd==x2, ea_align == 0 and (imm_val % 4) == 2,
|
|
// opcode:lhu op1:x13; dest:x2; immval:-0x556; align:0
|
|
TEST_LOAD(x7,x1,0,x13,x2,-0x556,8,lhu,0)
|
|
|
|
inst_3:
|
|
// rs1==x4, rd==x11, ea_align == 0 and (imm_val % 4) == 3,
|
|
// opcode:lhu op1:x4; dest:x11; immval:-0x5; align:0
|
|
TEST_LOAD(x7,x1,0,x4,x11,-0x5,12,lhu,0)
|
|
|
|
inst_4:
|
|
// rs1==x8, rd==x5, ea_align == 2 and (imm_val % 4) == 0,
|
|
// opcode:lhu op1:x8; dest:x5; immval:0x80; align:2
|
|
TEST_LOAD(x7,x1,0,x8,x5,0x80,16,lhu,2)
|
|
|
|
inst_5:
|
|
// rs1==x6, rd==x10, imm_val == 0,
|
|
// opcode:lhu op1:x6; dest:x10; immval:0x0; align:0
|
|
TEST_LOAD(x7,x1,0,x6,x10,0x0,20,lhu,0)
|
|
|
|
inst_6:
|
|
// rs1==x10, rd==x1, ea_align == 2 and (imm_val % 4) == 1,
|
|
// opcode:lhu op1:x10; dest:x1; immval:0x9; align:2
|
|
TEST_LOAD(x7,x2,0,x10,x1,0x9,24,lhu,2)
|
|
RVTEST_SIGBASE( x3,signature_x3_0)
|
|
|
|
inst_7:
|
|
// rs1==x1, rd==x13, ea_align == 2 and (imm_val % 4) == 2,
|
|
// opcode:lhu op1:x1; dest:x13; immval:-0xa; align:2
|
|
TEST_LOAD(x3,x2,0,x1,x13,-0xa,0,lhu,2)
|
|
|
|
inst_8:
|
|
// rs1==x14, rd==x4, ea_align == 2 and (imm_val % 4) == 3,
|
|
// opcode:lhu op1:x14; dest:x4; immval:-0x11; align:2
|
|
TEST_LOAD(x3,x2,0,x14,x4,-0x11,4,lhu,2)
|
|
|
|
inst_9:
|
|
// rs1==x11, rd==x8,
|
|
// opcode:lhu op1:x11; dest:x8; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x2,0,x11,x8,-0x800,8,lhu,0)
|
|
|
|
inst_10:
|
|
// rs1==x5, rd==x12,
|
|
// opcode:lhu op1:x5; dest:x12; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x2,0,x5,x12,-0x800,12,lhu,0)
|
|
|
|
inst_11:
|
|
// rs1==x9, rd==x7,
|
|
// opcode:lhu op1:x9; dest:x7; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x2,0,x9,x7,-0x800,16,lhu,0)
|
|
|
|
inst_12:
|
|
// rs1==x12, rd==x15,
|
|
// opcode:lhu op1:x12; dest:x15; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x4,0,x12,x15,-0x800,20,lhu,0)
|
|
|
|
inst_13:
|
|
// rs1==x7, rd==x0,
|
|
// opcode:lhu op1:x7; dest:x0; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x4,0,x7,x0,-0x800,24,lhu,0)
|
|
|
|
inst_14:
|
|
// rs1==x2, rd==x14,
|
|
// opcode:lhu op1:x2; dest:x14; immval:-0x800; align:0
|
|
TEST_LOAD(x3,x4,0,x2,x14,-0x800,28,lhu,0)
|
|
RVTEST_SIGBASE( x1,signature_x1_0)
|
|
|
|
inst_15:
|
|
// rd==x6,
|
|
// opcode:lhu op1:x14; dest:x6; immval:-0x800; align:0
|
|
TEST_LOAD(x1,x4,0,x14,x6,-0x800,0,lhu,0)
|
|
#endif
|
|
|
|
|
|
RVTEST_CODE_END
|
|
RVMODEL_HALT
|
|
|
|
RVTEST_DATA_BEGIN
|
|
.align 4
|
|
rvtest_data:
|
|
.word 0xbabecafe
|
|
RVTEST_DATA_END
|
|
|
|
RVMODEL_DATA_BEGIN
|
|
|
|
|
|
signature_x7_0:
|
|
.fill 0*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x7_1:
|
|
.fill 7*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x3_0:
|
|
.fill 8*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x1_0:
|
|
.fill 1*(XLEN/32),4,0xdeadbeef
|
|
|
|
#ifdef rvtest_mtrap_routine
|
|
|
|
mtrap_sigptr:
|
|
.fill 64*(XLEN/32),4,0xdeadbeef
|
|
|
|
#endif
|
|
|
|
#ifdef rvtest_gpr_save
|
|
|
|
gpr_save:
|
|
.fill 32*(XLEN/32),4,0xdeadbeef
|
|
|
|
#endif
|
|
|
|
RVMODEL_DATA_END
|