forked from Github_Repos/cvw
56 lines
2.5 KiB
Systemverilog
56 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// privpiperegs.sv
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//
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// Written: David_Harris@hmc.edu 12 May 2022
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// Modified:
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//
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// Purpose: Pipeline registers for early exceptions
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//
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// Documentation: RISC-V System on Chip Design Chapter 5
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module privpiperegs (
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input logic clk, reset,
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input logic StallD, StallE, StallM,
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input logic FlushD, FlushE, FlushM,
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input logic InstrPageFaultF, InstrAccessFaultF, // instruction faults
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input logic IllegalIEUInstrFaultD, // illegal IEU instruction decoded
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output logic InstrPageFaultM, InstrAccessFaultM, // delayed instruction faults
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output logic IllegalIEUInstrFaultM // delayed illegal IEU instruction
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);
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// Delayed fault signals
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logic InstrPageFaultD, InstrAccessFaultD;
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logic InstrPageFaultE, InstrAccessFaultE;
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logic IllegalIEUInstrFaultE;
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// pipeline fault signals
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flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
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{InstrPageFaultF, InstrAccessFaultF},
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{InstrPageFaultD, InstrAccessFaultD});
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flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE,
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{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD},
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE});
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flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM,
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE},
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM});
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endmodule |