forked from Github_Repos/cvw
a4907b5d29
An ITLB miss concurrent with a d cache flush did not interlock. The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
3 lines
92 B
Plaintext
3 lines
92 B
Plaintext
1. [ ] AMO should always generate store faults never load faults. We are generating both.
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