forked from Github_Repos/cvw
89 lines
3.3 KiB
Systemverilog
89 lines
3.3 KiB
Systemverilog
///////////////////////////////////////////
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// alu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: RISC-V Arithmetic/Logic Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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input logic [4:0] alucontrol,
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output logic [WIDTH-1:0] result,
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output logic [2:0] flags);
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logic [WIDTH-1:0] condinvb, presum, sum, shift, slt, sltu, bor;
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logic right, arith, w64;
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logic carry, zero, neg;
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logic lt, ltu;
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logic overflow;
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// addition
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assign condinvb = alucontrol[3] ? ~b : b;
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assign {carry, presum} = a + condinvb + {{(WIDTH-1){1'b0}},alucontrol[3]};
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// support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
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generate
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if (WIDTH==64)
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assign sum = w64 ? {{32{presum[31]}}, presum[31:0]} : presum;
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else
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assign sum = presum;
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endgenerate
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// shifts
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assign arith = alucontrol[3]; // sra
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assign w64 = alucontrol[4];
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assign right = (alucontrol[2:0] == 3'b101); // sra or srl
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shifter #(WIDTH) sh(a, b[5:0], right, arith, w64, shift);
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// OR optionally passes zero when ALUControl[3] is set, supporting lui
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assign bor = alucontrol[3] ? b : a|b;
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// condition code flags based on add/subtract output
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assign zero = (sum == 0);
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assign neg = sum[WIDTH-1];
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// overflow occurs when the numbers being added have the same sign
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// and the result has the opposite sign
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assign overflow = (a[WIDTH-1] ~^ condinvb[WIDTH-1]) & (a[WIDTH-1] ^ sum[WIDTH-1]);
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assign lt = neg ^ overflow;
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assign ltu = ~carry;
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assign flags = {zero, lt, ltu};
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// slt
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assign slt = {{(WIDTH-1){1'b0}}, lt};
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assign sltu = {{(WIDTH-1){1'b0}}, ltu};
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always_comb
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case (alucontrol[2:0])
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3'b000: result = sum; // add or sub
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3'b001: result = shift; // sll
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3'b010: result = slt; // slt
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3'b011: result = sltu; // sltu
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3'b100: result = a ^ b; // xor
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3'b101: result = shift; // sra or srl
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3'b110: result = bor; // or / pass through input b for lui
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3'b111: result = a & b; // and
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endcase
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endmodule
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