Shreya Sanghai bbe0957df5 Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do		2021-03-18 17:25:48 -04:00
..
regression-wally.py	Undo accidental change	2021-03-16 18:16:00 -04:00
sim-busybear
sim-busybear-batch	busybear: make a second .do file with better optimization for command line mode	2021-03-08 19:35:00 +00:00
sim-wally
sim-wally-batch	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
sim-wally-rv32ic	add rv32ic regression test	2021-03-11 12:40:29 -05:00
wally-busybear-batch.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-busybear.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-coremark_bare.do	Switched coremark to RV64IM	2021-03-17 22:39:56 -05:00
wally-coremark.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-peripherals-signals.do	refactored sim file	2021-03-05 14:25:16 -05:00
wally-peripherals.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined-batch.do	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
wally-pipelined-ross.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined.do	Temporarily reverted my last few commits	2021-03-17 15:16:01 -05:00
wave-all.do
wave.do	Merge branch 'gshare' into main	2021-03-18 17:25:48 -04:00