forked from Github_Repos/cvw
400 lines
12 KiB
Systemverilog
400 lines
12 KiB
Systemverilog
///////////////////////////////////////////
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// riscvsingle.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Simplified Single Cycle RISC-V Processor
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// Adapted from DDCA RISC-V Edition
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// Modified to match partitioning in RISC-V SoC Design
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// run 210
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// Expect simulator to print "Simulation succeeded"
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// when the value 25 (0x19) is written to address 100 (0x64)
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// Single-cycle implementation of RISC-V (RV32I)
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// User-level Instruction Set Architecture V2.2
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// Implements a subset of the base integer instructions:
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// lw, sw
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// add, sub, and, or, slt
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// addi, andi, ori, slti
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// beq
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// jal
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// Exceptions, traps, and interrupts not implemented
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// little-endian memory
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// 31 32-bit registers x1-x31, x0 hardwired to 0
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// R-Type instructions
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// add, sub, and, or, slt
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// INSTR rd, rs1, rs2
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// Instr[31:25] = funct7 (funct7b5 & opb5 = 1 for sub, 0 for others)
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// I-Type Instructions
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// lw, I-type ALU (addi, andi, ori, slti)
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// lw: INSTR rd, imm(rs1)
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// I-type ALU: INSTR rd, rs1, imm (12-bit signed)
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// Instr[31:20] = imm[11:0]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// S-Type Instruction
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// sw rs2, imm(rs1) (store rs2 into address specified by rs1 + immm)
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// Instr[31:25] = imm[11:5] (offset[11:5])
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// Instr[24:20] = rs2 (src)
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// Instr[19:15] = rs1 (base)
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:0] (offset[4:0])
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// Instr[6:0] = opcode
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// B-Type Instruction
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// beq rs1, rs2, imm (PCTarget = PC + (signed imm x 2))
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// Instr[31:25] = imm[12], imm[10:5]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:1], imm[11]
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// Instr[6:0] = opcode
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// J-Type Instruction
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// jal rd, imm (signed imm is multiplied by 2 and added to PC, rd = PC+4)
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// Instr[31:12] = imm[20], imm[10:1], imm[11], imm[19:12]
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// Instruction opcode funct3 funct7
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// add 0110011 000 0000000
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// sub 0110011 000 0100000
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// and 0110011 111 0000000
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// or 0110011 110 0000000
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// slt 0110011 010 0000000
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// addi 0010011 000 immediate
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// andi 0010011 111 immediate
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// ori 0010011 110 immediate
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// slti 0010011 010 immediate
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// beq 1100011 000 immediate
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// lw 0000011 010 immediate
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// sw 0100011 010 immediate
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// jal 1101111 immediate immediate
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/* verilator lint_on UNUSED */
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/* verilator lint_off COMBDLY */
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/* verilator lint_off INITIALDLY */
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/* verilator lint_off STMTDLY */
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module testbench();
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logic clk;
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logic reset;
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logic [31:0] WriteData, IEUAdr;
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logic MemWrite;
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// instantiate device to be tested
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riscvsinglecore dut(clk, reset, WriteData, IEUAdr, MemWrite);
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// initialize test
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initial begin
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reset <= 1; # 22; reset <= 0;
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end
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// generate clock to sequence tests
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always begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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// check results
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always @(negedge clk) begin
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if(MemWrite) begin
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if(IEUAdr === 100 & WriteData === 25) begin
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$display("Simulation succeeded");
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$stop;
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end else if (IEUAdr !== 96) begin
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$display("Simulation failed");
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$stop;
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end
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end
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end
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endmodule
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module riscvsinglecore(
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input logic clk, reset,
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output logic [31:0] WriteData, IEUAdr,
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output logic MemWrite);
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logic [31:0] PC, PCPlus4, Instr, ReadData;
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logic PCSrc;
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ifu ifu(.clk, .reset, .PCSrc, .IEUAdr, .Instr, .PC, .PCPlus4);
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ieu ieu(.clk, .reset, .Instr, .PC, .PCPlus4, .PCSrc, .MemWrite, .IEUAdr, .WriteData, .ReadData);
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lsu lsu(.clk, .MemWrite, .IEUAdr, .WriteData, .ReadData);
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endmodule
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module ifu(
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input logic clk, reset,
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input logic PCSrc,
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input logic [31:0] IEUAdr,
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output logic [31:0] Instr, PC, PCPlus4);
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logic [31:0] PCNext;
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// next PC logic
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flopr #(32) pcreg(clk, reset, PCNext, PC);
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adder pcadd4(PC, 32'd4, PCPlus4);
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mux2 #(32) pcmux(PCPlus4, IEUAdr, PCSrc, PCNext);
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irom irom(PC, Instr);
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endmodule
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module irom(input logic [31:0] a,
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output logic [31:0] rd);
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logic [31:0] RAM[63:0];
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initial
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$readmemh("riscvtest.memfile",RAM);
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assign rd = RAM[a[7:2]]; // word aligned
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endmodule
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module ieu(
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input logic clk, reset,
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input logic [31:0] Instr,
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input logic [31:0] PC, PCPlus4,
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output logic PCSrc, MemWrite,
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output logic [31:0] IEUAdr, WriteData,
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input logic [31:0] ReadData);
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logic RegWrite, Jump, Eq, ALUResultSrc, ResultSrc;
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logic [1:0] ALUSrc, ImmSrc;
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logic [1:0] ALUControl;
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controller c(.Op(Instr[6:0]), .Funct3(Instr[14:12]), .Funct7b5(Instr[30]), .Eq,
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.ALUResultSrc, .ResultSrc, .MemWrite, .PCSrc,
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.ALUSrc, .RegWrite, .ImmSrc, .ALUControl);
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datapath dp(.clk, .reset, .Funct3(Instr[14:12]),
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.ALUResultSrc, .ResultSrc, .ALUSrc, .RegWrite, .ImmSrc, .ALUControl, .Eq,
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.PC, .PCPlus4, .Instr, .IEUAdr, .WriteData, .ReadData);
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endmodule
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module controller(
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input logic [6:0] Op,
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input logic Eq,
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input logic [2:0] Funct3,
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input logic Funct7b5,
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output logic ALUResultSrc,
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output logic ResultSrc,
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output logic MemWrite,
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output logic PCSrc,
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output logic RegWrite,
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output logic [1:0] ALUSrc, ImmSrc,
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output logic [1:0] ALUControl);
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logic Branch, Jump;
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logic Sub, ALUOp;
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logic [10:0] controls;
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// Main decoder
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always_comb
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case(Op)
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// RegWrite_ImmSrc_ALUSrc_ALUOp_ALUResultSrc_MemWrite_ResultSrc_Branch_Jump
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7'b0000011: controls = 11'b1_00_01_0_0_0_1_0_0; // lw
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7'b0100011: controls = 11'b0_01_01_0_0_1_0_0_0; // sw
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7'b0110011: controls = 11'b1_xx_00_1_0_0_0_0_0; // R-type
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7'b0010011: controls = 11'b1_00_01_1_0_0_0_0_0; // I-type ALU
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7'b1100011: controls = 11'b0_10_11_0_0_0_0_1_0; // beq
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7'b1101111: controls = 11'b1_11_11_0_1_0_0_0_1; // jal
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default: controls = 11'bx_xx_xx_x_x_x_x_x_x; // non-implemented instruction
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endcase
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assign {RegWrite, ImmSrc, ALUSrc, ALUOp, ALUResultSrc, MemWrite,
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ResultSrc, Branch, Jump} = controls;
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// ALU Control Logic
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assign Sub = ALUOp & ((Funct3 == 3'b000) & Funct7b5 & Op[5] | (Funct3 == 3'b010)); // subtract or SLT
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assign ALUControl = {Sub, ALUOp};
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// PCSrc logic
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assign PCSrc = Branch & Eq | Jump;
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endmodule
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module datapath(
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input logic clk, reset,
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input logic [2:0] Funct3,
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input logic ALUResultSrc, ResultSrc,
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input logic [1:0] ALUSrc,
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input logic RegWrite,
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input logic [1:0] ImmSrc,
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input logic [1:0] ALUControl,
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output logic Eq,
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input logic [31:0] PC, PCPlus4,
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input logic [31:0] Instr,
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output logic [31:0] IEUAdr, WriteData,
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input logic [31:0] ReadData);
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logic [31:0] ImmExt;
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logic [31:0] R1, R2, SrcA, SrcB;
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logic [31:0] ALUResult, IEUResult, Result;
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// register file logic
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regfile rf(.clk, .WE3(RegWrite), .A1(Instr[19:15]), .A2(Instr[24:20]),
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.A3(Instr[11:7]), .WD3(Result), .RD1(R1), .RD2(R2));
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extend ext(.Instr(Instr[31:7]), .ImmSrc, .ImmExt);
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// ALU logic
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cmp cmp(.R1, .R2, .Eq);
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mux2 #(32) srcamux(R1, PC, ALUSrc[1], SrcA);
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mux2 #(32) srcbmux(R2, ImmExt, ALUSrc[0], SrcB);
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alu alu(.SrcA, .SrcB, .ALUControl, .Funct3, .ALUResult, .IEUAdr);
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mux2 #(32) ieuresultmux(ALUResult, PCPlus4, ALUResultSrc, IEUResult);
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mux2 #(32) resultmux(IEUResult, ReadData, ResultSrc, Result);
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assign WriteData = R2;
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endmodule
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module regfile(
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input logic clk,
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input logic WE3,
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input logic [ 4:0] A1, A2, A3,
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input logic [31:0] WD3,
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output logic [31:0] RD1, RD2);
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logic [31:0] rf[31:1];
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// three ported register file
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// read two ports combinationally (A1/RD1, A2/RD2)
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// write third port on rising edge of clock (A3/WD3/WE3)
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// register 0 hardwired to 0
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always_ff @(posedge clk)
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if (WE3) rf[A3] <= WD3;
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assign RD1 = (A1 != 0) ? rf[A1] : 0;
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assign RD2 = (A2 != 0) ? rf[A2] : 0;
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endmodule
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module extend(
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input logic [31:7] Instr,
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input logic [1:0] ImmSrc,
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output logic [31:0] ImmExt);
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always_comb
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case(ImmSrc)
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// I-type
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2'b00: ImmExt = {{20{Instr[31]}}, Instr[31:20]};
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// S-type (stores)
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2'b01: ImmExt = {{20{Instr[31]}}, Instr[31:25], Instr[11:7]};
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// B-type (branches)
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2'b10: ImmExt = {{20{Instr[31]}}, Instr[7], Instr[30:25], Instr[11:8], 1'b0};
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// J-type (jal)
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2'b11: ImmExt = {{12{Instr[31]}}, Instr[19:12], Instr[20], Instr[30:21], 1'b0};
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default: ImmExt = 32'bx; // undefined
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endcase
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endmodule
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module cmp(
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input logic [31:0] R1, R2,
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output logic Eq
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);
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assign Eq = (R1 == R2);
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endmodule
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module alu(
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input logic [31:0] SrcA, SrcB,
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input logic [1:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [31:0] ALUResult, IEUAdr);
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logic [31:0] CondInvb, Sum, SLT;
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logic ALUOp, Sub, Overflow, Neg, LT;
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logic [2:0] ALUFunct;
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assign {Sub, ALUOp} = ALUControl;
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// Add or subtract
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assign CondInvb = Sub ? ~SrcB : SrcB;
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assign Sum = SrcA + CondInvb + Sub;
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assign IEUAdr = Sum; // Send this out to IFU and LSU
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// Set less than based on subtraction result
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assign Overflow = (SrcA[31] ^ SrcB[31]) & (SrcA[31] ^ Sum[31]);
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assign Neg = Sum[31];
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assign LT = Neg ^ Overflow;
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assign SLT = {31'b0, LT};
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assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
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always_comb
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case (ALUFunct)
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3'b000: ALUResult = Sum; // add or sub
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3'b010: ALUResult = SLT; // slt
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3'b110: ALUResult = SrcA | SrcB; // or
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3'b111: ALUResult = SrcA & SrcB; // and
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default: ALUResult = 'x;
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endcase
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endmodule
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module lsu(
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input logic clk, MemWrite,
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input logic [31:0] IEUAdr, WriteData,
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output logic [31:0] ReadData);
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logic [31:0] RAM[63:0];
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assign ReadData = RAM[IEUAdr[7:2]]; // word aligned
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always_ff @(posedge clk)
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if (MemWrite) RAM[IEUAdr[7:2]] <= WriteData;
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endmodule
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module flopr #(parameter WIDTH = 8) (
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input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= 0;
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else q <= d;
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endmodule
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module adder(input [31:0] a, b,
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output [31:0] y);
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assign y = a + b;
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endmodule
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