forked from Github_Repos/cvw
956 lines
58 KiB
ArmAsm
956 lines
58 KiB
ArmAsm
///////////////////////////////////////////
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//
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// WALLY-plic
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//
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// Author: Nicholas Lucio <nlucio@hmc.edu>
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//
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// Created 2022-06-16
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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RVTEST_ISA("RV32I")
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
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INIT_TESTS
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TRAP_HANDLER m
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j run_test_loop // begin test loop/table tests instead of executing inline code.
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INIT_TEST_TABLE
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END_TESTS
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TEST_STACK_AND_DATA
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.align 2
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test_cases:
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# ---------------------------------------------------------------------------------------------
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# Test Contents
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#
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# Here is where the actual tests are held, or rather, what the actual tests do.
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# each entry consists of 3 values that will be read in as follows:
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#
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# '.4byte [x28 Value], [x29 Value], [x30 value]'
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# or
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# '.4byte [address], [value], [test type]'
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#
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# The encoding for x30 test type values can be found in the test handler in the framework file
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#
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# ---------------------------------------------------------------------------------------------
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# =========== Define PLIC registers ===========
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.equ PLIC, 0x0C000000
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.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
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.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
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.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
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.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
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.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
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.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
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.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0
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.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode)
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.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1
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# =========== Define GPIO registers ===========
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.equ GPIO, 0x10060000
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.equ input_val, (GPIO+0x00)
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.equ input_en, (GPIO+0x04)
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.equ output_en, (GPIO+0x08)
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.equ output_val, (GPIO+0x0C)
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.equ rise_ie, (GPIO+0x18)
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.equ rise_ip, (GPIO+0x1C)
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.equ fall_ie, (GPIO+0x20)
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.equ fall_ip, (GPIO+0x24)
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.equ high_ie, (GPIO+0x28)
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.equ high_ip, (GPIO+0x2C)
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.equ low_ie, (GPIO+0x30)
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.equ low_ip, (GPIO+0x34)
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.equ iof_en, (GPIO+0x38)
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.equ iof_sel, (GPIO+0x3C)
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.equ out_xor, (GPIO+0x40)
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# =========== Define UART registers ===========
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.equ UART, 0x10000000
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.equ UART_IER, (UART+0x01)
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.equ UART_MCR, (UART+0x04)
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.equ UART_MSR, (UART+0x06)
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# =========== Initialize UART and GPIO ===========
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# GPIO Initialization
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.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en
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.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en
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.4byte output_val, 0x00000000, write32_test # make sure output_val is 0
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.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts
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# =========== Initialize relevant PLIC registers ===========
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.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
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.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
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.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
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.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
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# =========== Machine-Mode Priority Testing (1.T.X) ===========
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# Test 1.0.0: GPIO int lacks priority (0 = 0)
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.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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#.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.0.1: GPIO int has priority (1 > 0)
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.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.0.2: meip and c/c clear without interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.1.0: GPIO lacks priority (1 = 1)
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.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.1.1: GPIO int has priority (2 > 1)
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.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.2.0: GPIO int lacks priority (2 = 2)
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.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.2.1: GPIO int has priority (3 > 2)
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.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.3.0: GPIO int lacks priority (3 = 3)
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.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.3.1: GPIO int has priority (4 > 3)
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.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.4.0: GPIO int lacks priority (4 = 4)
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.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.4.1: GPIO int has priority (5 > 4)
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.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.5.0: GPIO int lacks priority (5 = 5)
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.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.5.1: GPIO int has priority (6 > 5)
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.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.6.0: GPIO int lacks priority (6 = 6)
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.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.6.1: GPIO int has priority (7 > 6)
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.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# Test 1.7.0: GPIO int lacks priority (7 = 7)
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.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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# =========== UART vs GPIO priority (2.X) ===========
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
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|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
|
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
|
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
|
|
# UART Initialization
|
|
.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS
|
|
.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0
|
|
.4byte UART_MSR, 0x00, write08_test # disable UART interrupt
|
|
|
|
# Test 2.0: GPIO Priority = UART Priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
|
|
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 2.1: GPIO Priority > UART Priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
|
|
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 2.2: GPIO Priority < UART Priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
|
|
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 2.3: GPIO Priority < UART Priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
|
|
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 2.4: Interrupts don't have enough priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
|
|
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
|
|
.4byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000000, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# =========== SEIP tests (3.X) ===========
|
|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
|
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
|
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
|
|
# Test 3.0: Cause machine and supervisor interrupts
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
|
|
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
|
|
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
|
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 3.1: Suppress machine mode interrupts
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
|
|
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
|
|
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
|
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 3.2: Cause SEIP with UART first
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
|
|
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
|
|
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
|
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 3.3: Low SEIP due to insufficient priority
|
|
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2
|
|
.4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3
|
|
.4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4
|
|
.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000000, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# =========== UART interrupt enable tests (4.X) ===========
|
|
|
|
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
|
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
|
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
|
|
|
# Test 4.0: GPIO m-mode disabled
|
|
|
|
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 4.1: UART m-mode disabled
|
|
|
|
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 4.2: GPIO s-mode disabled
|
|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000A00, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 4.3: UART s-mode disabled
|
|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 4.4: GPIO and UART s-mode disabled
|
|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000800, readmip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 4.5: GPIO and UART m-mode disabled
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.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
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.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
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.4byte 0x0, 0x00000200, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 4.6: GPIO and UART fully disabled
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.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
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.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
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.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
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.4byte 0x0, 0x00000200, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# =========== GPIO interrupt enable tests (5.X) ===========
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.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
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.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
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.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
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.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
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# Test 5.0: GPIO m-mode disabled
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.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000200, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.1: UART m-mode disabled
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.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000A00, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.2: GPIO s-mode disabled
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.3: UART s-mode disabled
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000A00, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.4: GPIO and UART s-mode disabled
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.5: GPIO and UART m-mode disabled
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.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000200, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# Test 5.6: GPIO and UART fully disabled
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.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
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.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000000, readmip_test # read mip
|
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
|
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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|
|
|
# =========== S-mode enable tests (7.X) ===========
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.4byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode
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.4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output
|
|
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
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.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
|
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
|
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
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|
|
|
# Test 7.0: GPIO m-mode disabled
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|
|
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.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
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.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
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|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
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.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.1: UART m-mode disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.2: GPIO s-mode disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.3: UART s-mode disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.4: GPIO and UART s-mode disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
|
|
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000000, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.5: GPIO and UART m-mode disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
|
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
|
|
.4byte 0x0, 0x00000200, readsip_test # read mip
|
|
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
|
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
|
|
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
|
|
.4byte output_val, 0x00000000, write32_test # clear output_val
|
|
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
|
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
|
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
|
|
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
|
|
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
|
|
|
|
# Test 7.6: GPIO and UART fully disabled
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|
|
|
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
|
|
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
|
|
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
|
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
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.4byte 0x0, 0x00000000, readsip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
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.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
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.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
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.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
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.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
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.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
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# =========== Special claim tests (8) ===========
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.4byte 0x0, 0x0, goto_m_mode # write 0x9 to output
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.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
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.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
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.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5
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# Test 8
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending
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.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO
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.4byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO
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.4byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set
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.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again
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.4byte 0x0, 0x00000000, readmip_test # meip is zeroed
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
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.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending
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.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
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.4byte 0x0, 0x0, terminate_test # terminate tests
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