forked from Github_Repos/cvw
452 lines
17 KiB
C
452 lines
17 KiB
C
/*
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* QEMU RISC-V VirtIO Board
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* RISC-V machine with 16550a UART and VirtIO MMIO
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-properties.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/virt.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_plic.h"
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#include "hw/misc/sifive_test.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/display/ramfb.h"
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static const MemMapEntry virt_memmap[] = {
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[VIRT_MROM] = { 0x1000, 0xf000 },
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[VIRT_CLINT] = { 0x2000000, 0x10000 },
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[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
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[VIRT_UART0] = { 0x10000000, 0x100 },
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[VIRT_DRAM] = { 0x80000000, 0x0 },
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};
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/* PCIe high mmio is fixed for RV32 */
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#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
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#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
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/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
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#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
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#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
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static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
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uint64_t mem_size, const char *cmdline, bool is_32_bit)
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{
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void *fdt;
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//int i, cpu, socket;
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int cpu, socket;
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MachineState *mc = MACHINE(s);
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uint64_t addr, size;
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uint32_t *clint_cells, *plic_cells;
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unsigned long clint_addr, plic_addr;
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uint32_t plic_phandle[MAX_NODES];
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uint32_t cpu_phandle, intc_phandle;
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uint32_t phandle = 1, plic_mmio_phandle = 1;
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char *mem_name, *cpu_name, *core_name, *intc_name;
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char *name, *clint_name, *plic_name, *clust_name;
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if (mc->dtb) {
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fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
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if (!fdt) {
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error_report("load_device_tree() failed");
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exit(1);
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}
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goto update_bootargs;
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} else {
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fdt = mc->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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if (is_32_bit) {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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} else {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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}
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(fdt, intc_name);
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intc_phandle = phandle++;
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qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(fdt, core_name);
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qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(fdt, mem_name);
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qemu_fdt_setprop_cells(fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
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g_free(mem_name);
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clint_addr = memmap[VIRT_CLINT].base +
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(memmap[VIRT_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(fdt, clint_name);
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qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
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g_free(clint_name);
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plic_phandle[socket] = phandle++;
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plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
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plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
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qemu_fdt_add_subnode(fdt, plic_name);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#address-cells", FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#interrupt-cells", FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
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plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, plic_name, "reg",
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0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
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riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
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qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
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g_free(plic_name);
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g_free(clint_cells);
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g_free(plic_cells);
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g_free(clust_name);
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}
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for (socket = 0; socket < riscv_socket_count(mc); socket++) {
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if (socket == 0) {
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plic_mmio_phandle = plic_phandle[socket];
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}
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}
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riscv_socket_fdt_write_distance_matrix(mc, fdt);
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name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
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qemu_fdt_add_subnode(fdt, name);
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qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
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qemu_fdt_setprop_cells(fdt, name, "reg",
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0x0, memmap[VIRT_UART0].base,
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0x0, memmap[VIRT_UART0].size);
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qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
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qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
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qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
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g_free(name);
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update_bootargs:
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if (cmdline) {
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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}
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static void virt_machine_init(MachineState *machine)
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{
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const MemMapEntry *memmap = virt_memmap;
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RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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char *plic_hart_config, *soc_name;
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size_t plic_hart_config_len;
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target_ulong start_addr = memmap[VIRT_DRAM].base;
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target_ulong firmware_end_addr, kernel_start_addr;
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uint32_t fdt_load_addr;
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uint64_t kernel_entry;
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DeviceState *mmio_plic;
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int i, j, base_hartid, hart_count;
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/* Check socket count limit */
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if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
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error_report("number of sockets/nodes should be less than %d",
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VIRT_SOCKETS_MAX);
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exit(1);
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}
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/* Initialize sockets */
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mmio_plic = NULL;
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for (i = 0; i < riscv_socket_count(machine); i++) {
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if (!riscv_socket_check_hartids(machine, i)) {
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error_report("discontinuous hartids in socket%d", i);
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exit(1);
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}
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base_hartid = riscv_socket_first_hartid(machine, i);
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if (base_hartid < 0) {
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error_report("can't find hartid base for socket%d", i);
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exit(1);
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}
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hart_count = riscv_socket_hart_count(machine, i);
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if (hart_count < 0) {
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error_report("can't find hart count for socket%d", i);
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exit(1);
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}
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soc_name = g_strdup_printf("soc%d", i);
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object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
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TYPE_RISCV_HART_ARRAY);
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g_free(soc_name);
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object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
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machine->cpu_type, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
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base_hartid, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
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hart_count, &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
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/* Per-socket CLINT */
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sifive_clint_create(
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memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
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memmap[VIRT_CLINT].size, base_hartid, hart_count,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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SIFIVE_CLINT_TIMEBASE_FREQ, true);
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/* Per-socket PLIC hart topology configuration string */
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plic_hart_config_len =
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(strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
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plic_hart_config = g_malloc0(plic_hart_config_len);
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for (j = 0; j < hart_count; j++) {
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if (j != 0) {
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strncat(plic_hart_config, ",", plic_hart_config_len);
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}
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strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
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plic_hart_config_len);
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plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
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}
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/* Per-socket PLIC */
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s->plic[i] = sifive_plic_create(
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memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
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plic_hart_config, base_hartid,
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VIRT_PLIC_NUM_SOURCES,
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VIRT_PLIC_NUM_PRIORITIES,
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VIRT_PLIC_PRIORITY_BASE,
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VIRT_PLIC_PENDING_BASE,
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VIRT_PLIC_ENABLE_BASE,
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VIRT_PLIC_ENABLE_STRIDE,
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VIRT_PLIC_CONTEXT_BASE,
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VIRT_PLIC_CONTEXT_STRIDE,
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memmap[VIRT_PLIC].size);
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g_free(plic_hart_config);
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/* Try to use different PLIC instance based device type */
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if (i == 0) {
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mmio_plic = s->plic[i];
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}
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}
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if (riscv_is_32bit(&s->soc[0])) {
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#if HOST_LONG_BITS == 64
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/* limit RAM size in a 32-bit system */
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if (machine->ram_size > 10 * GiB) {
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machine->ram_size = 10 * GiB;
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error_report("Limiting RAM size to 10 GiB");
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}
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#endif
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}
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
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riscv_is_32bit(&s->soc[0]));
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
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memmap[VIRT_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
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mask_rom);
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if (riscv_is_32bit(&s->soc[0])) {
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firmware_end_addr = riscv_find_and_load_firmware(machine,
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"opensbi-riscv32-generic-fw_dynamic.bin",
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start_addr, NULL);
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} else {
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firmware_end_addr = riscv_find_and_load_firmware(machine,
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"opensbi-riscv64-generic-fw_dynamic.bin",
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start_addr, NULL);
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}
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if (machine->kernel_filename) {
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kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
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firmware_end_addr);
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kernel_entry = riscv_load_kernel(machine->kernel_filename,
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kernel_start_addr, NULL);
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = riscv_load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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qemu_fdt_setprop_cell(machine->fdt, "/chosen",
|
|
"linux,initrd-start", start);
|
|
qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
|
|
end);
|
|
}
|
|
} else {
|
|
/*
|
|
* If dynamic firmware is used, it doesn't know where is the next mode
|
|
* if kernel argument is not set.
|
|
*/
|
|
kernel_entry = 0;
|
|
}
|
|
|
|
/* Compute the fdt load address in dram */
|
|
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
|
|
machine->ram_size, machine->fdt);
|
|
/* load the reset vector */
|
|
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
|
|
virt_memmap[VIRT_MROM].base,
|
|
virt_memmap[VIRT_MROM].size, kernel_entry,
|
|
fdt_load_addr, machine->fdt);
|
|
|
|
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
|
|
0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
|
|
serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
|
|
|
}
|
|
|
|
static void virt_machine_instance_init(Object *obj)
|
|
{
|
|
}
|
|
|
|
static void virt_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "RISC-V VirtIO board";
|
|
mc->init = virt_machine_init;
|
|
mc->max_cpus = VIRT_CPUS_MAX;
|
|
mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
|
|
mc->pci_allow_0_address = true;
|
|
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
|
|
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
|
|
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
|
|
mc->numa_mem_supported = true;
|
|
|
|
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
|
|
}
|
|
|
|
static const TypeInfo virt_machine_typeinfo = {
|
|
.name = MACHINE_TYPE_NAME("virt"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = virt_machine_class_init,
|
|
.instance_init = virt_machine_instance_init,
|
|
.instance_size = sizeof(RISCVVirtState),
|
|
};
|
|
|
|
static void virt_machine_init_register_types(void)
|
|
{
|
|
type_register_static(&virt_machine_typeinfo);
|
|
}
|
|
|
|
type_init(virt_machine_init_register_types)
|
|
|