forked from Github_Repos/cvw
182 lines
9.4 KiB
Systemverilog
Executable File
182 lines
9.4 KiB
Systemverilog
Executable File
`include "wally-config.vh"
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module fctrl (
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
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input logic [6:0] OpD, // bits 6:0 of instruction
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input logic [4:0] Rs2D, // bits 24:20 of instruction
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input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode
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input logic [2:0] FRM_REGW, // rounding mode from CSR
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input logic [1:0] STATUS_FS, // is FPU enabled?
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic FRegWriteD, // FP register write enable
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output logic FDivStartD, // Start division or squareroot
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output logic [1:0] FResSelD, // select result to be written to fp register
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output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit
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output logic [1:0] PostProcSelD,
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output logic [`FMTBITS-1:0] FmtD, // precision - single-0 double-1
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output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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output logic FWriteIntD // is the result written to the integer register
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);
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`define FCTRLW 11
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logic [`FCTRLW-1:0] ControlsD;
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//*** will putting x for don't cares reduce area in synthisis???
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// FPU Instruction Decoder
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1;
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else case(OpD)
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flw
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3'b011: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // fld
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsw
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3'b011: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsd
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0; // fmsub
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7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0; // fnmsub
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7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0; // fnmadd
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7'b1010011: casez(Funct7D)
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7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0; // fadd
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7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0; // fsub
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7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0; // fmul
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0; // fdiv
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7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0; // fsqrt
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7'b00100??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1; // non-implemented instruction
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endcase
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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7'b1101000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.s.w w->s
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.s.wu wu->s
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.s.l l->s
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.s.lu lu->s
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endcase
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7'b1100000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.s s->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.s s->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.s s->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.s s->lu
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endcase
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7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.w.x to fp reg
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7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0; // fcvt.s.d
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7'b1101001: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.d.w w->d
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.d.wu wu->d
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2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.d.l l->d
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2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.d.lu lu->d
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endcase
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7'b1100001: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.d d->w
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2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.d d->wu
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.d d->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.d d->lu
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endcase
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.d.x to fp reg
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7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0; // fcvt.d.s
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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// unswizzle control bits
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assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, FOpCtrlD, FDivStartD, IllegalFPUInstrD} = ControlsD;
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// rounding modes:
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// 000 - round to nearest, ties to even
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// 001 - round twords 0 - round to min magnitude
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// 010 - round down - round twords negitive infinity
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// 011 - round up - round twords positive infinity
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// 100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
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// 111 - dynamic - choose FRM_REGW as rounding mode
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assign FrmD = &Funct3D ? FRM_REGW : Funct3D;
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// Precision
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// 0-single
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// 1-double
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if (`FPSIZES == 1)
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assign FmtD = 0;
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else if (`FPSIZES == 2)begin
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logic [1:0] FmtTmp;
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assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
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assign FmtD = (`FMT == FmtTmp);
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end
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else if (`FPSIZES == 3|`FPSIZES == 4)
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assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
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// Final Res Sel:
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// fp int
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// 00 other cmp
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// 01 postproc cvt
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// 10 store class
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// 11 mv
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// post processing Sel:
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// 00 cvt
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// 01 div
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// 10 fma
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// Other Sel:
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// Ctrl signal = {FOpCtrl[2], &FOpctrl[1:0]}
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// 000 - sign 00
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// 001 - negate sign 00
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// 010 - xor sign 00
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// 011 - mv to fp 01
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// 110 - min 10
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// 101 - max 10
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// OpCtrl:
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// Fma: {not multiply-add?, negate prod?, negate Z?}
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// 000 - fmadd
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// 001 - fmsub
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// 010 - fnmsub
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// 011 - fnmadd
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// 100 - mul
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// 110 - add
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// 111 - sub
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// Div:
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// 0 - ???
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// 1 - ???
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// Cvt Int: {Int to Fp?, 64 bit int?, signed int?}
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// Cvt Fp: output format
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// 10 - to half
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// 00 - to single
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// 01 - to double
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// 11 - to quad
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// Cmp: {equal?, less than?}
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// 010 - eq
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// 001 - lt
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// 011 - le
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// 110 - min
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// 101 - max
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// Sgn:
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// 00 - sign
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// 01 - negate sign
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// 10 - xor sign
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endmodule
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