forked from Github_Repos/cvw
53 lines
1.4 KiB
Systemverilog
53 lines
1.4 KiB
Systemverilog
module testbench();
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logic clk, reset;
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logic a, b, c, s, cout, sexpected, coutexpected;
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logic [31:0] vectornum, errors;
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logic [4:0] testvectors[10000:0];
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// instantiate device under test
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fulladder dut(a, b, c, s, cout);
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// generate clock
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always
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begin
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clk = 1; #5; clk = 0; #5;
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end
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// at start of test, load vectors and pulse reset
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initial
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begin
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$readmemb("fulladder.tv", testvectors);
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vectornum = 0; errors = 0;
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reset = 1; #22; reset = 0;
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk)
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begin
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#1; {a, b, c, coutexpected, sexpected} = testvectors[vectornum];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if (s !== sexpected | cout !== coutexpected) begin // check result
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$display("Error: inputs = %b", {a, b, c});
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$display(" outputs cout s = %b%b (%b%b expected)",cout, s, coutexpected, sexpected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 5'bx) begin
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$display("%d tests completed with %d errors",
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vectornum, errors);
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$stop;
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end
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end
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endmodule
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module fulladder(input logic a, b, c,
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output logic s, cout);
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assign s = a ^ b ^ c;
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assign cout = (a & b) | (a & c) | (b & c);
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endmodule
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