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Configurable RISC-V Processor
23 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
b08b86f561
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Noah Boorstin b08b86f561 sucessfully simulate first 30 instructions 
still need to find a better solution to InstrAccessFault/DataAccessFault though
2021-01-23 19:01:44 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined sucessfully simulate first 30 instructions 2021-01-23 19:01:44 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor