forked from Github_Repos/cvw
474 lines
14 KiB
Python
Executable File
474 lines
14 KiB
Python
Executable File
#!/usr/bin/python3
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##################################
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# testgen-TVEC.py (new)
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#
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# dottolia@hmc.edu 1 Mar 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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#
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#
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##################################
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# DOCUMENTATION:
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#
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# The most up-to-date comments explaining what everything
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# does and the layout of the privileged tests
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# can be found in testgen-TVAL.py. This and
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# other files do not have as many comments
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#
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###################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# setup
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##################################
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areVectoredTrapsSupported = True
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##################################
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# functions
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##################################
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#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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reg3 = randint(1,20)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return str(reg1), str(reg2), str(reg3)
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def writeVectors(storecmd, returningInstruction):
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global testnum
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# Illegal Instruction
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# writeTest(storecmd, f, r, f"""
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# .fill 1, 4, 0
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# """, False, 0)
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# # Breakpoint
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# if returningInstruction != "ebreak":
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# writeTest(storecmd, f, r, f"""
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# ebreak
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# """, False, 0)
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# # Load Address Misaligned
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# writeTest(storecmd, f, r, f"""
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# lw x0, 11(x0)
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# """, False, 0)
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# # Load Access fault: False, 5
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# # Store/AMO address misaligned
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# writeTest(storecmd, f, r, f"""
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# sw x0, 11(x0)
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# """, False, 0)
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# # Environment call from u-mode: only for when only M and U mode enabled?
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# # writeTest(storecmd, f, r, f"""
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# # ecall
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# # """, False, 8, "u")
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if returningInstruction != "ecall":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 0)
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if fromMode == "m" and testMode == "m":
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expectedCode = 7 if fromMode == "m" else 5
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clintAddr = "0x2004000"
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writeTest(storecmd, f, r, f"""
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li x1, 0x8
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csrrs x0, {fromMode}status, x1
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la x18, {clintAddr}
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# lw x11, 0(x18)
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# li x1, 0x3fffffffffffffff
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# {storecmd} x1, 0(x18)
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li x1, 0x80
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csrrs x0, {fromMode}ie, x1
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{storecmd} x0, 0(x18)
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""", True, expectedCode, f"""
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li x1, 0x80
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csrrc x0, {fromMode}ie, x1
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li x1, 0x8
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csrrc x0, {fromMode}status, x1
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la x18, {clintAddr}
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{storecmd} x0, 0(x18)
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""")
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# Instruction page fault: 12
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# Load page fault: 13
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# Store/AMO page fault: 15
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def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testnum, storeAddressOffset, xlen
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expected = code
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# Boilerplate
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#
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# x28 is the address that our trap handler will jump to before returning.
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# This is where we can do our actual tests. After we're done computing and storing
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# what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
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#
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lines = f"""
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la x28, _jtest{testnum}
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j _jdo{testnum}
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_jtest{testnum}:
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nop
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{resetHander}
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jr x27
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_jdo{testnum}:
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li x25, 0xDEADBEA7
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{test}
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"""
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if not areVectoredTrapsSupported or not vectoredInterrupts:
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expected = 0
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writeGeneralTest(storecmd, f, r, lines, expected)
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def writeGeneralTest(storecmd, f, r, test, expected):
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global testnum, storeAddressOffset, xlen
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lines = f"""
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{test}
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{storecmd} x25, {testnum * wordsize}(x6)
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"""
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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testCount = 4;
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# setup
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# Change this seed to a different constant value for every test
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seed(0xC363DAEB9193AB45) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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# testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
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for testMode in ["m", "s"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + "TVEC"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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storeAddressOffset = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# Ensure MODE of *tvec (last 2 bits) is either 00 or 01
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f.write(f"""
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csrr x19, {testMode}tvec
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""")
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for i in range(0, 16):
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i = i;
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trySet = i | 0b10;
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expected = trySet & 0xFFFF_FFFFD;
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writeGeneralTest(storecmd, f, r, f"""
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li x1, {trySet}
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csrw {testMode}tvec, x1
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csrr x25, {testMode}tvec
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""", expected)
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f.write(f"""
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csrw {testMode}tvec, x19
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""")
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# We need to leave at least one bit in medeleg unset so that we have a way to get
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# back to machine mode when the tests are complete (otherwise we'll only ever be able
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# to get up to supervisor mode).
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#
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# So, we define a returning instruction which will be used to cause the exception that
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# brings us into machine mode. The bit for this returning instruction is NOT set in
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# medeleg. However, this also means that we can't test that instruction. So, we have
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# two different returning instructions.
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#
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# Current code is written to only support ebreak and ecall.
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#
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# For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
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# returning instruction. For others, like testgen-CAUSE, we'll need to put
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# both ebreak and ecall here.
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for returningInstruction in ["ebreak"]:
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for vectoredInterrupts in [True, False]:
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x28: address trap handler should jump to for the test
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# x27: address the test should return to after the test
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# ...
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# x25: value to write to memory
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# ...
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# x20: intermediate value in trap handler. Don't overwrite this!
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value (currently unused — user mode traps deprecated)
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# x16: mideleg old value
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# ...
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# x10 - x14 can be freely written
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# ...
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# x7: copy of x6. Increment this instead of using an offset on x6.
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# this allows us to create more than 2048/wordlen tests.
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# Set up x7 and store old value of mtvec
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lines = f"""
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# add x7, x6, x0
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csrr x19, mtvec
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"""
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# Not used — user mode traps are deprecated
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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# Code that will jump to the test (x28 is set in writeTest above)
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testJumpCode = f"""
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auipc x27, 0
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addi x27, x27, 12
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jr x28
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"""
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beforeCode = {"m": "", "s": ""}
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for pm in ["m", "s"]:
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for i in range(0, 16):
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beforeCode[pm] = beforeCode[pm] + f"""
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nop
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nop
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li x25, {i}
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j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts}
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"""
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# Code for handling traps in different modes
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# Some comments are inside of the below strings (prefixed with a #, as you might expected)
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enableVectored = "addi x1, x1, 1" if vectoredInterrupts else ""
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lines += f"""
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# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
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li x30, 0
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# Set up
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la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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# csrw utvec, x1 # user mode traps are not supported
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# Start the tests!
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j _j_t_begin_{returningInstruction}_{vectoredInterrupts}
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# Machine mode traps
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_j_m_trap_{returningInstruction}_{vectoredInterrupts}:
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{beforeCode['m']}
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_j_m_trap_end_{returningInstruction}_{vectoredInterrupts}:
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{testJumpCode}
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts}
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mret
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# Supervisor mode traps
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_j_s_trap_{returningInstruction}_{vectoredInterrupts}:
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{beforeCode['s']}
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_j_s_trap_end_{returningInstruction}_{vectoredInterrupts}:
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{testJumpCode}
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csrrs x20, sepc, x0
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addi x20, x20, 4
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csrrw x0, sepc, x20
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bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
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sret
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# Unused: user mode traps are no longer supported
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_j_u_trap_{returningInstruction}_{vectoredInterrupts}:
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{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
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csrrs x20, uepc, x0
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addi x20, x20, 4
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csrrw x0, uepc, x20
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bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}
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uret
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# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
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# want to implement this, you'll likely need to reset sedeleg here
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# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
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_j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}:
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j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
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_j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}:
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li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking...
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{returningInstruction} # ... this instruction!
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# Run the actual tests!
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_j_t_begin_{returningInstruction}_{vectoredInterrupts}:
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"""
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fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
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# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
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medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
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# Set medeleg and mideleg
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lines += f"""
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csrr x18, medeleg
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li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
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csrw medeleg, x9
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csrr x16, mideleg
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li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
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csrw mideleg, x9
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"""
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f.write(lines)
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for fromMode in fromModeOptions:
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lines = ""
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# Code to bring us down to supervisor mode
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if fromMode == "s" or fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x31, mstatus, x1
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li x1, 0b0100000000000
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csrrs x31, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in supervisor mode...
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"""
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# Code to bring us down to user mode
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if fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x31, sstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the sret instruction
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csrw sepc, x1
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sret
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# We're now in user mode...
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"""
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f.write(lines)
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for i in range(0,testCount):
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writeVectors(storecmd, returningInstruction)
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# Very end of test. Bring us back up to machine mode
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# We set x30 to 1, which will cause us to branch to _j_all_end in the
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# machine mode trap handler, before executing the mret instruction. This will
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# make us stay in machine mode.
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#
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# If we're currently in user mode, this will first bump us up to the supervisor mode
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# trap handler, which will call returningInstruction again before it's sret instruction,
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# bumping us up to machine mode
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#
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# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
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f.write(f"""
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li x30, 1
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li gp, 0
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{returningInstruction}
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_j_all_end_{returningInstruction}_{vectoredInterrupts}:
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# Reset trap handling csrs to old values
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csrw mtvec, x19
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csrw medeleg, x18
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csrw mideleg, x16
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""")
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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