forked from Github_Repos/cvw
440 lines
19 KiB
Systemverilog
440 lines
19 KiB
Systemverilog
///////////////////////////////////////////
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// testbench.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the riscv-arch-test and Imperas suites
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module testbench;
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parameter DEBUG=0;
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logic clk;
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logic reset_ext, reset;
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logic [`XLEN-1:0] testadr, testadrNoBase;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [3:0] dummy;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [`PA_BITS-1:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic [`XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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logic DCacheFlushDone, DCacheFlushStart;
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string testName;
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string memfilename, pathname, adrstr;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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logic SDCCLK;
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logic SDCCmdIn;
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic [3:0] SDCDatIn;
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tri1 [3:0] SDCDat;
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tri1 SDCCmd;
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logic HREADY;
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logic HSELEXT;
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logic InitializingMemories;
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integer ResetCount, ResetThreshold;
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logic InReset;
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// Imperas look here.
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initial
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begin
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ResetCount = 0;
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ResetThreshold = 2;
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InReset = 1;
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testadr = 0;
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testadrNoBase = 0;
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//testName = "rv64i_m/I/src/add-01.S";
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testName = "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S";
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//pathname = "../../tests/riscof/work/riscv-arch-test/";
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pathname = "../../tests/riscof/work/wally-riscv-arch-test/";
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memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
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if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else $error("Imperas test bench requires BUS.");
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ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
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// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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end
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rvviTrace rvviTrace();
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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if(`EXT_MEM_SUPPORTED) begin
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ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
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.HWSTRB);
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end else begin
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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end
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if(`FPGA) begin : sdcard
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sdModel sdcard
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(.sdClk(SDCCLK),
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.cmd(SDCCmd),
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.dat(SDCDat));
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assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
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assign SDCCmdIn = SDCCmd;
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assign SDCDatIn = SDCDat;
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end else begin
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assign SDCCmd = '0;
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assign SDCDat = '0;
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end
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wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
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.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
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dut.core.ifu.FinalInstrRawF[31:0],
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dut.core.ifu.InstrD, dut.core.ifu.InstrE,
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dut.core.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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// if ($time % 100000 == 0) $display("Time is %0t", $time);
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end
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// check results
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assign reset_ext = InReset;
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always @(negedge clk)
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begin
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InitializingMemories = 0;
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if(InReset == 1) begin
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// once the test inidicates it's done we need to immediately hold reset for a number of cycles.
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if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
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else begin // hit reset threshold so we remove reset.
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InReset = 0;
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ResetCount = 0;
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end
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end
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end // always @ (negedge clk)
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// track the current function or global label
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if (DEBUG == 1) begin : FunctionName
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FunctionName FunctionName(.reset(reset),
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.clk(clk),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// Termination condition
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// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
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// or sw gp,-56(t0) for new Imperas tests
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// or sd gp, -56(t0)
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// or on a jump to self infinite loop (6f) for RISC-V Arch tests
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logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
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if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
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else assign ecf = 0;
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assign DCacheFlushStart = ecf &
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(dut.core.ieu.dp.regf.rf[3] == 1 |
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(dut.core.ieu.dp.regf.we3 &
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dut.core.ieu.dp.regf.a3 == 3 &
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dut.core.ieu.dp.regf.wd3 == 1)) |
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((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
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DCacheFlushFSM DCacheFlushFSM(.clk(clk),
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.reset(reset),
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.start(DCacheFlushStart),
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.done(DCacheFlushDone));
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// initialize the branch predictor
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if (`BPRED_ENABLED == 1)
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begin
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genvar adrindex;
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// Initializing all zeroes into the branch predictor memory.
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for(adrindex = 0; adrindex < 1024; adrindex++) begin
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initial begin
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force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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#1;
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release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
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release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
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end
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end
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end
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// check for hange up.
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logic [`XLEN-1:0] OldPCW;
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integer WatchDogTimerCount;
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localparam WatchDogTimerThreshold = 1000000;
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logic WatchDogTimeOut;
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always_ff @(posedge clk) begin
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OldPCW <= PCW;
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if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
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else WatchDogTimerCount = '0;
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end
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always_comb begin
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WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
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if(WatchDogTimeOut) begin
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$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
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$stop;
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end
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end
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endmodule
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module riscvassertions;
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initial begin
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assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
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assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
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assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
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assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
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assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
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assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
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assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
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assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
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assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
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assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
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assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
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assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
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assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
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assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
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assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
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assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
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assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
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assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
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assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
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assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
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assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
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assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
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assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
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assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
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assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
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assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
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assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
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assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
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assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
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assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
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assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
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assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
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assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
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end
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// *** DH 8/23/
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module DCacheFlushFSM
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(input logic clk,
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input logic reset,
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input logic start,
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output logic done);
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genvar adr;
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logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
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if(`DCACHE) begin
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localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
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localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
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localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
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localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
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localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
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localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
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//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
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localparam integer numwords = sramlen/`XLEN;
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localparam integer lognumlines = $clog2(numlines);
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localparam integer loglinebytelen = $clog2(linebytelen);
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localparam integer lognumways = $clog2(numways);
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localparam integer tagstart = lognumlines + loglinebytelen;
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genvar index, way, cacheWord;
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logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [sramlen-1:0] cacheline;
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logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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for(index = 0; index < numlines; index++) begin
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for(way = 0; way < numways; way++) begin
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for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
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copyShadow #(.tagstart(tagstart),
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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copyShadow(.clk,
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.start,
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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// these dirty bit selections would be needed if dirty is moved inside the tag array.
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
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.index(index),
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.cacheWord(cacheWord),
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.CacheData(CacheData[way][index][cacheWord]),
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.CacheAdr(CacheAdr[way][index][cacheWord]),
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.CacheTag(CacheTag[way][index][cacheWord]),
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.CacheValid(CacheValid[way][index][cacheWord]),
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.CacheDirty(CacheDirty[way][index][cacheWord]));
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end
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end
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end
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integer i, j, k, l;
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always @(posedge clk) begin
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if (start) begin #1
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#1
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for(i = 0; i < numlines; i++) begin
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for(j = 0; j < numways; j++) begin
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for(l = 0; l < cachesramwords; l++) begin
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if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
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for(k = 0; k < numwords; k++) begin
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//cacheline = CacheData[j][i][0];
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// does not work with modelsim
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// # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
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// see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
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//ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
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ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
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end
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end
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end
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end
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end
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end
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end
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end
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flop #(1) doneReg(.clk, .d(start), .q(done));
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endmodule
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module copyShadow
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#(parameter tagstart, loglinebytelen, sramlen)
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(input logic clk,
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input logic start,
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input logic [`PA_BITS-1:tagstart] tag,
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input logic valid, dirty,
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input logic [sramlen-1:0] data,
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input logic [32-1:0] index,
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input logic [32-1:0] cacheWord,
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output logic [sramlen-1:0] CacheData,
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output logic [`PA_BITS-1:0] CacheAdr,
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output logic [`XLEN-1:0] CacheTag,
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output logic CacheValid,
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output logic CacheDirty);
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always_ff @(posedge clk) begin
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if(start) begin
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CacheTag = tag;
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CacheValid = valid;
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CacheDirty = dirty;
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CacheData = data;
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CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
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end
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end
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endmodule
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task automatic updateProgramAddrLabelArray;
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input string ProgramAddrMapFile, ProgramLabelMapFile;
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inout integer ProgramAddrLabelArray [string];
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// Gets the memory location of begin_signature
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integer ProgramLabelMapFP, ProgramAddrMapFP;
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ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
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ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
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if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
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while (!$feof(ProgramLabelMapFP)) begin
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string label, adrstr;
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integer returncode;
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returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
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returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
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if (ProgramAddrLabelArray.exists(label))
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ProgramAddrLabelArray[label] = adrstr.atohex();
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end
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end
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$fclose(ProgramLabelMapFP);
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$fclose(ProgramAddrMapFP);
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endtask
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