Ross Thompson ae4a55471d Oups fixed order of ending swap with mux between cache and fetch buffer.		2022-09-07 16:29:47 -05:00
..
atomic.sv	Updated the names of the *WriteDataM inside the LSU to more meaningful names.	2022-08-23 10:34:39 -05:00
bigendianswap.sv	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
dtim.sv	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
interlockfsm.sv	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
lrsc.sv
lsu.sv	Oups fixed order of ending swap with mux between cache and fetch buffer.	2022-09-07 16:29:47 -05:00
lsuvirtmen.sv	Updated the names of the *WriteDataM inside the LSU to more meaningful names.	2022-08-23 10:34:39 -05:00
subwordread.sv	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
subwordwrite.sv	clean up subword write.	2022-09-01 17:55:19 -05:00
swbytemask.sv	Simplified swbytemask	2022-08-25 17:32:16 -07:00