forked from Github_Repos/cvw
347 lines
16 KiB
Systemverilog
347 lines
16 KiB
Systemverilog
///////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage core logic
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// Contains data cache, DTLB, subword read/write datapath, interface to external bus
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM,
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic TrapM,
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input logic FlushDCacheM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DCacheMiss,
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output logic DCacheAccess,
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataM,
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic DTLBFlushM,
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
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// connect to ahb
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr,
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(* mark_debug = "true" *) output logic LSUBusRead,
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(* mark_debug = "true" *) output logic LSUBusWrite,
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(* mark_debug = "true" *) input logic LSUBusAck,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA,
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(* mark_debug = "true" *) output logic [2:0] LSUBusSize,
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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output logic [`XLEN-1:0] PTE,
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output logic [1:0] PageType,
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output logic ITLBWriteF,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
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);
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logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache
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logic [`XLEN+1:0] IEUAdrExtM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic [1:0] LSURWM;
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logic [1:0] PreLSURWM;
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logic [2:0] LSUFunct3M;
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logic [6:0] LSUFunct7M;
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logic [1:0] LSUAtomicM;
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(* mark_debug = "true" *) logic [`PA_BITS-1:0] PreLSUPAdrM, LocalLSUBusAdr;
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logic [11:0] PreLSUAdrE, LSUAdrE;
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logic CPUBusy;
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logic MemReadM;
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logic DCacheStallM;
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logic CacheableM;
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logic SelHPTW;
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logic BusStall;
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logic InterlockStall;
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logic IgnoreRequest;
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logic BusCommittedM, DCacheCommittedM;
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////////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW and Interlock FSM (only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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////////////////////////////////////////////////////////////////////////////////////////////////
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
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// *** encapsulate as lsuvirtmem
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logic AnyCPUReqM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic HPTWRead;
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logic [2:0] HPTWSize;
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logic SelReplayCPURequest;
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assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
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interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM,
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.InterlockStall, .SelReplayCPURequest, .SelHPTW,
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.IgnoreRequest);
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hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
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.ITLBMissF(ITLBMissF & ~TrapM),
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.DTLBMissM(DTLBMissM & ~TrapM),
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.PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
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.HPTWReadPTE(ReadDataM),
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.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize);
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// arbiter between IEU and hptw
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// multiplex the outputs to LSU
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mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
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mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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end // if (`MEM_VIRTMEM)
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else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0;
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assign IgnoreRequest = TrapM;
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assign CPUBusy = StallW;
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assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM;
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end
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// **** look into this confusing signal.
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// This signal is confusing. CommittedM tells the CPU's trap unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. This signal is only low for the first cycle of a memory
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// operation.
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// **** I think there is also a bug here. Data cache misses and TLB misses both
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// set this bit in the first cycle. It is not strickly wrong, but it may be better
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// to flush the memory operation at that time.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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// MMU and Misalignment fault logic required if privileged unit exists
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if(`ZICSR_SUPPORTED == 1) begin : dmmu
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(SelHPTW),
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.PAdr(PreLSUPAdrM),
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.VAdr(IEUAdrM),
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.Size(LSUFunct3M[1:0]),
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.PTE,
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.PageTypeWriteVal(PageType),
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.TLBWrite(DTLBWriteM),
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.TLBFlush(DTLBFlushM),
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.PhysicalAddress(LSUPAdrM),
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.TLBMiss(DTLBMissM),
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.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
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.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
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.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), // **** change this to just use PreLSURWM
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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// *** lsumisaligned lsumisaligned(Funct3M, IEUAdrM, MemRW, LoadMisalignedFaultM, StoreAmoMisalignedFaultM);
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// *** lump into lsumislaigned module
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// Determine if an Unaligned access is taking place
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// hptw guarantees alignment, only check inputs from IEU.
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// *** modify MMU to put out LoadMisalignedFault and StoreMisalignedFault rather than DataMisalignedM
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end else begin
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assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
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assign LSUPAdrM = PreLSUPAdrM;
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assign CacheableM = '1;
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end
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Hart Memory System
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// Either Data Cache or Data Tightly Integrated Memory or just bus interface
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////////////////////////////////////////////////////////////////////////////////////////////////
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localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
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localparam integer LINELEN = `MEM_DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
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localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
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localparam integer LINEBYTELEN = LINELEN/8;
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localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
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logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] PreLSUBusHWDATA;
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logic [`XLEN-1:0] ReadDataWordM;
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logic [LINELEN-1:0] DCacheMemWriteData;
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logic [`XLEN-1:0] ReadDataWordMuxM;
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logic [`PA_BITS-1:0] DCacheBusAdr;
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logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0];
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logic DCacheWriteLine;
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logic DCacheFetchLine;
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logic DCacheBusAck;
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logic SelUncachedAdr;
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if (`MEM_DTIM) begin : dtim
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/* Consider restructuring with higher level blocks. Try drawing block diagrams with several pages of schematics,
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one for top level, one for each sublevel, alternate with either dtim or bus. If this looks more satisfactory,
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restructure code accordingly.
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dtim dtim (.clk, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM,
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.BusStallM, .LSUBusWrite, .LSUBusRead, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr,
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.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .DCacheWriteLine, .DCacheFetchLine, .DCacheBusAdr,
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.ReadDataLineSetsM, .DCacheMiss, .DCacheAccess); */
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// *** adjust interface so write address doesn't need delaying; switch to standard RAM?
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simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.clk,
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.a(CPUBusy | LSURWM[0] ? IEUAdrM[31:0] : IEUAdrE[31:0]),
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.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap.
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.wd(FinalWriteDataM), .rd(ReadDataWordM));
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;
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assign ReadDataWordMuxM = ReadDataWordM;
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assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
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assign ReadDataLineSetsM[0] = 0;
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assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
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end else begin : bus
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// replace from here up to if (`MEM_DCACHE) with busdp ***
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// Bus Side logic
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// register the fetch data from the next level of memory.
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// This register should be necessary for timing. There is no register in the uncore or
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// ahblite controller between the memories and this cache.
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logic [LOGWPL-1:0] WordCount;
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
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.d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
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end
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assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ;
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assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
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assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; // only in lsu, not ifu
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// exclude the subword write for uncached. We don't read the data first so we cannot
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// select the subword by masking. Subword write also exists inside the uncore to
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// suport subword masking for i/o. I'm not sure if this is necessary.
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assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA; // only in lsu, not ifu
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assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : (`XLEN == 32 ? 3'b010 : 3'b011); // ifu: always the XLEN value.
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// select between dcache and direct from the BUS. Always selected if no dcache.
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mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
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.d1(DCacheMemWriteData[`XLEN-1:0]),
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.s(SelUncachedAdr),
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.y(ReadDataWordMuxM));
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busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
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busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
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.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead,
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.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
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if(`MEM_DCACHE) begin : dcache
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
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dcache(.clk, .reset, .CPUBusy,
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.RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LSUAtomicM : 2'b00),
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.NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
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.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStallM),
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.CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData),
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.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
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end else begin : passthrough
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assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
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assign ReadDataLineSetsM[0] = 0;
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assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
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end
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end
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// sub word selection for read and writes and optional amo alu.
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subwordread subwordread(.ReadDataWordMuxM,
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.LSUPAdrM(LSUPAdrM[2:0]),
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.Funct3M(LSUFunct3M),
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.ReadDataM);
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// this might only get instantiated if there is a dcache or dtim.
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// There is a copy in the ebu. *** is it needed there, or can data come in from ebu, get muxed here and sent back out
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// Explore changing feedback path from output of AMOALU to subword write ***
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subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
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.HADDRD(LSUPAdrM[2:0]),
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.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
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.HWDATAIN(FinalAMOWriteDataM),
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.HWDATA(FinalWriteDataM));
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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////////////////////////////////////////////////////////////////////////////////////////////////
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if (`A_SUPPORTED) begin:lrsc
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/*atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .MemRead, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
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.SquashSCM, .LSURWM, ... ); *** */
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logic [`XLEN-1:0] AMOResult;
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amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
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.SquashSCW, .LSURWM);
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end else begin:lrsc
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assign SquashSCW = 0;
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assign LSURWM = PreLSURWM;
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assign FinalAMOWriteDataM = WriteDataM;
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end
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endmodule
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