forked from Github_Repos/cvw
51 lines
2.0 KiB
Systemverilog
51 lines
2.0 KiB
Systemverilog
///////////////////////////////////////////
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// comparator.sv
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//
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// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
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// Created: 8 December 2021
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// Modified:
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//
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// Purpose: Branch comparison
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// This comparator is best
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module comparator_dc_flip #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b, // Operands
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input logic sgnd, // Signed operands
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output logic [1:0] flags); // Output flags: {eq, lt}
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logic eq, lt; // Flags: equal (eq), less than (lt)
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logic [WIDTH-1:0] af, bf; // Operands with msb flipped (inverted) when signed
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// For signed numbers, flip most significant bit
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assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
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assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
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// Behavioral description gives best results
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assign eq = (a == b); // eq = 1 when operands are equal, 0 otherwise
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assign lt = (af < bf); // lt = 1 when a less than b (taking signed operands into account)
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assign flags = {eq, lt};
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endmodule
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