forked from Github_Repos/cvw
97 lines
2.0 KiB
ArmAsm
97 lines
2.0 KiB
ArmAsm
// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fence.i instruction of the RISC-V Zifencei extension.
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//
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#include "model_test.h"
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#include "arch_test.h"
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# Test Virtual Machine (TVM) used by program.
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RVTEST_ISA("RV64I")
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# Test code region
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
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#ifdef TEST_CASE_1
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RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*); check ISA:=regex(.*Zifencei.*); def TEST_CASE_1=True", fencei)
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# ---------------------------------------------------------------------------------------------
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RVMODEL_IO_WRITE_STR(x31, "# Test part A - test fence\n");
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# Addresses for test data and results
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la x16, test_A_data
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la x17, test_A_res
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# Register initialization
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li x3, 0
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# Load testdata
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lw x1, 0(x16)
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lw x2, 4(x16)
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# Test
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la x20, instr_A_src
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la x21, instr_A_dst
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lw x15, 0(x20)
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sw x15, 0(x21)
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fence.i
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instr_A_dst:
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lui x2, 0
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# Store results
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sw x1, 0(x17)
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sw x2, 4(x17)
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sw x3, 8(x17)
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sw x15, 12(x17)
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//
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// Assert
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//
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RVMODEL_IO_ASSERT_GPR_EQ(x17, x2, 0x00000012)
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RVMODEL_IO_ASSERT_GPR_EQ(x17, x3, 0x00000042)
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RVMODEL_IO_ASSERT_GPR_EQ(x17, x15, 0x001101B3)
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RVMODEL_IO_WRITE_STR(x31, "# Test part A1 - Complete\n");
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RVMODEL_IO_WRITE_STR(x31, "# Test End\n")
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#endif
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# ---------------------------------------------------------------------------------------------
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# HALT
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RVMODEL_HALT
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RVTEST_CODE_END
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RVTEST_DATA_BEGIN
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# Input data section.
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.data
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.align 4
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instr_A_src:
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add x3, x2, x1
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test_A_data:
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.word 0x30
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.word 0x12
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RVTEST_DATA_END
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# Output data section.
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RVMODEL_DATA_BEGIN
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test_A_res:
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.fill 4, 4, 0xdeadbeef
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32), 4, 0xdeadbeef
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#endif
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RVMODEL_DATA_END
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