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Configurable RISC-V Processor
1,725 Commits 14 Branches 1 Tag 31 MiB
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C 27.2%
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Python 2.7%
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James E. Stine a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
2021-10-06 08:26:09 -05:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
wally-pipelined Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
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LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor